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Unformatted text preview: Name Computer Architecture EE 4720 Midterm Examination Friday, 25 October 2002, 10:4011:30 CDT Alias Problem 1 (30 pts) Problem 2 (13 pts) Problem 3 (13 pts) Problem 4 (44 pts) Exam Total (100 pts) Good Luck! Problem 1: A new MIPS branch instruction, bieq rt,(rs) disp (branch indirect equal) compares a register value to a memory location, if they are equal the branch is taken. The target is computed in the same way as other branches. In the code below, the contents of register $s1 is compared to the contents of the memory location at address $s2 . Like all MIPS control transfers, bieq has one delay slot. [30 pts] ( a ) Modify the pipeline so that it can execute this new instruction. Show comparison units, multiplexors, and wires. Do not show control logic. For partial credt replace bieq ... with bneq $s1,$s2, LOOP . Use as much existing hardware as possible. Do not add a new memory port. The change should not reduce the clock frequency. Include the comparison unit for the branch condition. Add bypass paths so that the code below executes as shown. Label bypass paths with the cycle in which they are used. Include existing and any added bypass paths. Label the path carrying the branch target address with the cycle in which it is used....
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