Midterm Examination 2006p2

Midterm Examination 2006p2 - Name Computer Architecture EE...

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Unformatted text preview: Name Computer Architecture EE 4720 Midterm Examination Wednesday, 29 March 2006, 11:4012:30 CST Alias Problem 1 (10 pts) Problem 2 (40 pts) Problem 3 (50 pts) Exam Total (100 pts) Good Luck! Problem 1: The MIPS code below runs on the illustrated implementation. [10 pts] Show the execution of the code below on the illustrated pipeline. format immed IR Addr 25:21 20:16 IF ID EX WB MEM rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC = 30 2 "0" + 15:0 25:0 29:26 29:0 0 1 # Cycle 1 2 3 4 5 6 7 8 lw r1, 0(r2) add r1, r1, 7 sw r1, 0(r2) # Cycle 1 2 3 4 5 6 7 8 Note: To keep the test from getting too long the following parts were not included on the original exam. There should be at least one stall. Think about the questions below for a few moments, then look at the problem on the next page. Is it possible to add bypass connections to eliminate the stall and gain performance? If bypasses wont work does that mean its impossible to eliminate the stall? 2 Problem 2: The five-stage MIPS implementation below has an ALU in the MX (new name for MEM) stage (connections for that ALU are shown bold) and what was the ALU in the EA (new name for EX) stage is now just an adder and is to be used only for loads and stores.stage is now just an adder and is to be used only for loads and stores....
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Midterm Examination 2006p2 - Name Computer Architecture EE...

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