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Unformatted text preview: ABSTRACT A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recov- ery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools. Categories and Subject Descriptors B7.1 [ INTEGRATED CIRCUITS ] Types and Design Styles Subjects: Microprocessors and microcomputers, B8.1 [ Perform- ance and Reliability ]: Reliability, Testing and Fault-Tolerance. General Terms Design, Reliability. Keywords Microprocessor, SPARC, microarchitecture, reliability, clock dis- tribution, unix server. 1. INTRODUCTION This 5th generation SPARC64 processor is designed for high end unix servers. Business mission critical servers must operate 24 hours x 7 days reliably. A high data integrity is especially im- portant since an undetected data error is the worst thing to happen that cast doubt on all outputs from the server. Since high end serv- ers use many processor chips, the MTBF requirement for each processor is much more stringent than the one for single processor workstations. That is why this processor is designed to detect er- rors in execution units and data paths and also to recover from those detected errors as much as practically possible. These high reliability requirements were not fully met with the previous proc- essors designed for unix servers. The improvement in performance without consuming too much power is the important goal of this processor development. The target was to achieve twice the performance with the equal or less power compare to the then current 4th generation SPARC64 proc- essor which runs at 563MHz and consumes about 50W. To achieve this goal, a new 130nm partially depleted SOI CMOS process is selected. Minimizing the risk of using the new semiconductor process and keep the design schedule as planned were also the important design considerations. For this reason, simpler and ro- bust circuit design is favored. Also a clocking scheme is chosen to reduce the work for timing closure by giving timing tuning flexi- bility to the designers. Most of the design CAD tools are in-house developed. They are enhanced to handle the side effects of PD SOI technology, most notably, timing variation due to the floating body effect. 2. IMPLEMENTATION OVERVIEW The 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains 191M transistors with 19M in logic circuits, measures 18.14mm x 15.99mm and is covered with 5,858 low alpha emission lead bumps of which 269 are for I/O signals. The system bus is 16 bytes wide and operates with a 260MHz clock. It achieves a peak bytes wide and operates with a 260MHz clock....
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.
- Spring '08