{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

This Set - 11-1 This Set 11-1 These slides do not give...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
11-1 11-1 This Set These slides do not give detailed coverage of the material. See class notes and solved problems (last page) for more information. Text covers multiple-issue machines in Chapter 4, but does not cover most of the topics presented here. Outline Multiple Issue Introduction Superscalar Machines VLIW Machine Sample Problems 11-1 EE 4720 Lecture Transparency. Formatted 11:22, 8 April 2005 from lsli11. 11-1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
11-2 11-2 Multiple Issue Multiple-Issue Machine: A processor that can sustain fetch and execution of more than one instruction per cycle. n-Way Processor: A multiple issue machine that can sustain execution of n instructions per cycle. Single-Issue Machine: A processor that can sustain execution of at most one instruction per cycle. A neologism for the type of processor covered in Chapter 3 and part of Chapter 4. Sustain Execution of n IPC: Achieve a CPI of 1 n for some code fragment ... ... written by a friendly programmer ... ... to avoid cache misses and otherwise avoid stalls. 11-2 EE 4720 Lecture Transparency. Formatted 11:22, 8 April 2005 from lsli11. 11-2
Background image of page 2
11-3 11-3 Types of Multiple Issue Machines Superscalar Processor: A multiple-issue machine that implements a conventional ISA (such as MIPS and SPARC). Code need not be recompiled. General-purpose processors were superscalar starting in early 1990’s. VLIW Processor: A multiple-issue machine that implements a VLIW ISA ... ... in which simultaneous execution considered. (More later.) Since VLIW ISAs are novel, code must be re-compiled. Idea developed in early 1980’s, ... ... so far used in special-purpose and stillborn commercial machines, ... ... and is being used in Intel’s next generation processor. Intel’s Itanium implements the Itanium (IA-64) VLIW ISA. (Name of ISA and implementations are both Itanium.) 11-3 EE 4720 Lecture Transparency. Formatted 11:22, 8 April 2005 from lsli11. 11-3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
11-4 11-4 Superscalar Machines n -Way Superscalar Machine Construction Start with a scalar, a.k.a. single-issue, machine. Duplicate hardware so that most parts can handle n instructions per cycle. Don’t forget about control and data hazards. 11-4 EE 4720 Lecture Transparency. Formatted 11:22, 8 April 2005 from lsli11. 11-4
Background image of page 4
11-5 11-5 Superscalar Difficulties Register File Scalar: 2 reads, 1 write per cycle. n -way: 2 n reads, n writes per cycle. Dependency Checking and Bypass Paths For ALU Instructions Scalar, about 4 comparisons per cycle. n -way, about n (2(2 n + n - 1) = 6 n 2 - 2 n comparisons. Loads-Use Stalls Scalar, only following instruction would have to stall (if dependent). n -way, up to the next 2 n - 1 instructions would have to stall (if dependent). 11-5 EE 4720 Lecture Transparency. Formatted 11:22, 8 April 2005 from lsli11.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}