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Unpipelined Implementation

Unpipelined Implementation - 06-1 MIPS Implementation 06-1...

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06-1 06-1 MIPS Implementation Material from Chapter 3 of H&P (for DLX). Material from Chapter 6 of P&H (for MIPS). Outline: (In this set.) Unpipelined DLX Implementation. (Diagram only.) Pipelined DLX and MIPS Implementations: Hardware, notation, hazards. Dependency Definitions. Data Hazards: Definitions, stalling, bypassing. Control Hazards: Squashing, one-cycle implementation. Outline: (Covered in class but not yet in set.) Operation of nonpipelined implementation, elegance and power of pipelined implementation. (See text.) Computation of CPI for program executing a loop. 06-1 EE 4720 Lecture Transparency. Formatted 11:07, 4 March 2005 from lsli06. 06-1 06-2 06-2 Unpipelined Implementation Instruction fetch Instruction decode/ register fetch Execute/ address calculation Memory access Write back B PC 4 ALU 16 32 Add Data memory Registers Sign extend Instruction memory M u x M u x M u x M u x Zero? Branch taken Cond NPC lmm ALU output IR A LMD FIGURE 3.1 The implementation of the DLX datapath allows every instruction to be executed in four or five clock cycles. 06-2 EE 4720 Lecture Transparency. Formatted 11:07, 4 March 2005 from lsli06. 06-2 06-3 06-3 Pipelined MIPS Implementation format immed IR Addr 25:21 20:16 IR IF ID EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg = =0 <0 E Z N NPC Note: diagram omits connections for some instructions. 06-3 EE 4720 Lecture Transparency. Formatted 11:07, 4 March 2005 from lsli06. 06-3 06-4 06-4 Pipeline Details Pipeline Segments a.k.a. Pipeline Stages Divide pipeline into segments . Each segment occupied by at most one instruction. At any time, different segments can be occupied by different instructions. Segments given names: IF, ID, EX, MEM, WB Sometimes MEM shortened to ME . 06-4 EE 4720 Lecture Transparency. Formatted 11:07, 4 March 2005 from lsli06. 06-4
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06-5 06-5 Pipeline Registers a.k.a. Pipeline Latches Registers separating pipeline segments. Written at end of each cycle. To emphasize role, drawn as part of dividing bars. Registers named using pair of segment names and register name. For example, IF/ID.IR , ID/EX.IR , ID/EX.A (used in text, notes). if id ir , id ex ir , id ex rs val (used in Verilog code). 06-5 EE 4720 Lecture Transparency. Formatted 11:07, 4 March 2005 from lsli06. 06-5 06-6 06-6 Pipeline Execution Diagram Pipeline Execution Diagram Diagram showing the pipeline segments that instructions occupy as they execute. Time on horizontal axis, instructions on vertical axis. Diagram shows where instruction is at a particular time. Cycle 0 1 2 3 4 5 6 add r1, r2, r3 IF ID EX MEM WB and r4, r5, r6 IF ID EX MEM WB lw r7, 8(r9) IF ID EX MEM WB A vertical slice ( e.g. , at cycle 3) shows processor activity at that time. In such a slice a segment should appear at most once ... ... if it appears more than once execution not correct ...
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