Unpipelined Implementation

Unpipelined Implementation - 06-1 06-1 MIPSImplementation

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Unformatted text preview: 06-1 06-1 MIPSImplementation MaterialfromChapter3ofH&P(forDLX). MaterialfromChapter6ofP&H(forMIPS). Outline:(Inthisset.) UnpipelinedDLXImplementation.(Diagramonly.) PipelinedDLXandMIPSImplementations:Hardware,notation,hazards. DependencyDefinitions. DataHazards:Definitions,stalling,bypassing. ControlHazards:Squashing,one-cycleimplementation. Outline:(Coveredinclassbutnotyetinset.) Operationofnonpipelinedimplementation,eleganceandpowerofpipelinedimplementation. (Seetext.) ComputationofCPIforprogramexecutingaloop. 06-1 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-1 06-2 06-2 UnpipelinedImplementation Instruction fetch Instruction decode/ register fetch Execute/ address calculation Memory access Write back B PC 4 A L U 1 6 3 2 A d d Data memory R e g is te r s S ig n e x te n d Instruction memory M u x M u x M u x M u x Zero? Branch taken Cond NPC lmm ALU output IR A L M D FIGURE 3.1 The implementation of the DLX datapath allows every instruction to be executed in four or five clock cycles. 06-2 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-2 06-3 06-3 PipelinedMIPSImplementation format immed IR Addr 25:21 20:16 IR IF ID EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg = =0 <0 E Z N NPC Note:diagramomitsconnectionsforsomeinstructions. 06-3 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-3 06-4 06-4 PipelineDetails PipelineSegments a.k.a. PipelineStages Dividepipelineinto segments . Eachsegmentoccupiedbyatmostoneinstruction. Atanytime,differentsegmentscanbeoccupiedbydifferentinstructions. Segmentsgivennames: IF,ID,EX,MEM,WB Sometimes MEM shortenedto ME . 06-4 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-4 06-5 06-5 PipelineRegisters a.k.a. PipelineLatches Registersseparatingpipelinesegments. Writtenatendofeachcycle. Toemphasizerole,drawnaspartofdividingbars. Registersnamedusingpairofsegmentnamesandregistername. Forexample, IF/ID.IR , ID/EX.IR , ID/EX.A (usedintext,notes). if id ir , id ex ir , id ex rs val (usedinVerilogcode). 06-5 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-5 06-6 06-6 PipelineExecutionDiagram PipelineExecutionDiagram Diagramshowingthepipelinesegmentsthatinstructionsoccupyastheyexecute. Timeonhorizontalaxis,instructionsonverticalaxis. Diagramshowswhereinstructionisataparticulartime. Cycle 1 2 3 4 5 6 addr1,r2,r3 IF ID EX MEMWB andr4,r5,r6 IF ID EX MEMWB lw r7,8(r9) IF ID EX MEMWB Averticalslice( e.g. ,atcycle3)showsprocessoractivityatthattime. Insuchaslice asegmentshouldappearatmostonce ... ... ifitappearsmorethanonceexecutionnotcorrect ... ... sinceasegmentcanonlyexecuteoneinstructionatatime. 06-6 EE4720LectureTransparency.Formatted11:07,4March2005fromlsli06. 06-6 06-7 06-7 InstructionDecodingandPipelineControl PipelineControl Settingcontrolinputstodevicesincluding ... ... multiplexorinputs ... ... functionforALU ... ... operationformemory...
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Unpipelined Implementation - 06-1 06-1 MIPSImplementation

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