ASM_solns_part1 - Solutions Synchronous Digital State...

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1 Solutions – Synchronous Digital State Machine Design ASM Chart Circuit Realization (Problems 1 – 4) 1. Traditional Method Excitation Equations Output Equations From ASM chart: I 1 , I 2 00 01 11 10 SA SB SB SC SC SB SA SD SB SB SC SA SA SA SA SD SB SB SB SB SA SC SA SB SB SD SB SA SB OUT2 OUT1 I2 I1 STATE C1 C0 SA 0 0 SB 0 1 SC 1 0 SD 11 0 00 01 11 10 I 1 I 2 C 1 C 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 00 01 11 10 0 1 1 0 10 02 CI C C C C C II C + =+ + + 1 00 01 11 10 I 1 I 2 C 1 C 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 01 11 10 0 1 1 0 1 2 CC C I C C I I + State Assignment Next State Table 1 1 0 1 1 1 1. OUT SA SB I CC CC I CC C I 1 1 1 0 1 1 2. OUT SA I SB CCI CC CC CI = +
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2 PLA Based Design Given the 4-input, 4-output, 8 AND-term PLA, we can realize the combinational circuit required for the state generator with it, and realize the output logic separately. Or we can challenge ourselves to see if all of the combinational logic for the state generator as well as the output can be realized entirely with the PLA. If you count all the AND terms that will be required to implement the latter, you will find that you need 12 AND gates; however, the PLA has only 8 AND gates.
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This note was uploaded on 08/02/2009 for the course ECE EE2006 taught by Professor Dr.kassim during the Fall '07 term at National University of Singapore.

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ASM_solns_part1 - Solutions Synchronous Digital State...

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