# Chapter5 - EE2006 Digital Design/S Ranganath V...

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EE2006 Digital Design/S Ranganath V - 1 V. Combinational Logic Circuits (MSI Elements) Introduction Binary adders ± Half adders, full adders, ripple adders. Magnitude comparators Decoders ± BCD to 7-segment decoders Encoders ± Priority encoders Multiplexers Tri-state logic elements Demultiplexers These circuit elements introduce a higher level of functionality in digital design compared to ‘low level’ gate-based design (e.g. C programming vs. assembly programming).

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EE2006 Digital Design/S Ranganath V - 2 Introduction A general digital circuit diagram Combinational circuit: output values are functions of present inputs only. Sequential circuit: output values are functions of a) present inputs and b) internal circuit states. The latter are functions of previous input values. Hence the output in sequential circuits depends on present and past values. This implies that sequential circuits must have memory. We will study MSI circuit elements that realize commonly used logic functions. This chapter combinational MSI circuits. Next, sequential MSI circuits. Outputs Inputs
EE2006 Digital Design/S Ranganath V - 3 Binary adders Half adders : Need to add bits {0,1} of i A and i B . Associate binary bit 0 logic value F (0) binary bit 1 logic value T (1) This leads to the truth table and circuit for binary addition: A i B i SUM i CARRY i+1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 ii i i i SUM AB A B =⊕ i i i B A CARRY = + 1 Half adder circuit Half adder circuits do not suffice for general addition because they do not include the carry bit from the previous stage of addition, e.g. Carry 0 1 1 0 A 0 1 1 0 B + 0 0 1 1 SUM 1 0 0 1 Full Adders :

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EE2006 Digital Design/S Ranganath V - 4 Full adders can use the carry bit from the previous stage of addition. A i B i C i S i C i+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 Full adder A i B i C i S i C i+1 Current bits carry-in from previous stg carry-out to next stg Current sum 1 1 1 1 1 Full adder Truth table 0 1 1 0 01 10 0 00 1 01 11 10 A i B i C i B i C i 0 0 0 1 11 0 00 1 01 11 10 A i SUM i C i+1 A i B i Full adder half adder half adder C i ) ( ) ( i i i i i i i i i i i i i i i i i i i i 1 i B A C B A B A B A C B A C B A C B A B A C + = + + = + + = + iii i ii i ii i i SUM ABC ABC A(BC BC) A(BC BC) A(B C) A(B C) =+++ =+ ++ =⊕ +⊕ Note: 1 + i C is not a MSOP, but less overall hardware is reqd. if we use this expr. It allows sharing of i i B A between i SUM and 1 + i C .
EE2006 Digital Design/S Ranganath V - 5 Parallel adders : (Ripple adders) Stage 3 FA A3 B3 S3 Stage 0 FA A0 B0 S0 Stage 2 FA A2 B2 S2 Stage 1 FA A1 B1 S1 C3 C2 C1 C0 0 C4 carry-out Note: no carry-in 4-bit parallel adder 4 FA’s cascaded to form a 4-bit adder. In general, N FA’s can be used to form a N-bit adder.

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Chapter5 - EE2006 Digital Design/S Ranganath V...

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