DD1 - VHDL BASIC VHDL FOR DIGITAL SYSTEMS DESIGN Copyright...

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VHDL DIGITAL design page 1 BASIC VHDL FOR DIGITAL SYSTEMS DESIGN © Copyright Ashraf Kassim . All rights reserved.
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VHDL DIGITAL design page 2 VHDL Introduction
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VHDL DIGITAL design page 3 What is VHDL ? VHDL stands for V HSIC H ardware D escription L anguage ( VHSIC : Very High Speed Integrated Circuits ) VHDL is high level programming language which is optimized for describing the behaviour of digital systems. VHDL is capable of describing concurrent events ( unlike other languages ) which is crucial for describing real circuits. VHDL is an IEEE Standard ( Std 1076-1987, Std 1076-1993 ). VHDL is one of many HDLs ( see self-reading material ).
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VHDL DIGITAL design page 4 Major Purposes of VHDL VHDL program Simulator Model Simulated / Actual Outputs Hardware
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VHDL DIGITAL design page 5 Major Purposes of VHDL A simulation modeling language: VHDL allows for describing behavior of electronic circuits ( from simple logic gates to complete μ Ps ) at high levels of detail . These simulation models can be used as building blocks in larger circuits. A specification language: VHDL can be used to capture the performance & interface requirements of each component in a large system including precise descriptions of functional & timing aspects ( e.g. rise time , fall time etc ). A design entry language: VHDL allows complex designs to be expressed as computer programs (some also allow for schematic entry as well). A verification language: VHDL can capture performance specification for a circuit in the form of test bench ( descriptions of circuit stimuli & corresponding expected outputs ) A synthesization language: VHDL 's structural features enable it to be used as a netlist language ( like EDIF ) for targeted implementation in CPLD , FPGA or ASIC .
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VHDL DIGITAL design page 6 Why VHDL ? Advantages: Shorter Design Cycles Improved Design Quality Vendor and Technology Independence Lower Design Cost Easy Design Management Disadvantages : Cost (incl. training) Debugging
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VHDL DIGITAL design page 7 VHDL CONCEPTS
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VHDL DIGITAL design page 8 Device modeling in VHDL : VHDL describes a model for a digital device by specifying: external view of device (entity) : interface through which it communicates with other models. internal views of device (architecture) : ( one or more ) specifies functionality or internal structure. binding (configuration) : specifies binding of one architecture body from others associated with entity EXTERNAL Device VIEW Model DIGITAL SYSTEM (at least one) INTERNAL VIEWS (Architecuture)
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VHDL DIGITAL design page 9 Entity Declaration Specifies entity name & interface ports but not internals Example : entity declaration for Half Adder : A X1 SUM A1 CARRY B entity HALF _ ADDER is port ( A , B : in std _ logic ; SUM, CARRY: out std _ logic ); end HALF _ ADDER; -- this is a comment line , after – upto end of line -- case-insensitive : CARRY,CarrY refer to same name -- entity HALF_ADDER has two input ports (A,B),
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DD1 - VHDL BASIC VHDL FOR DIGITAL SYSTEMS DESIGN Copyright...

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