# DD2 - SEQUENTIAL CIRCUITS SEQUENTIAL cIRCUITS Copyright...

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SEQUENTIAL CIRCUITS DIGITAL design page 2 Sequential Circuits: An Overview In sequential circuits, outputs depend on both present & past inputs. We consider sequential circuits and their realizations. Types of sequential circuits: Synchronous and Asynchronous : Clocked : need a clock input Unclocked responds to inputs at discrete time instants governed by a clock input responds whenever input signals change flip-flops ( FF s): set-reset (SR) FF s & applications ( FF s) come with clocked circuits: J-K , D , and T FF s, and conversions between them. Design and realization of asynchronous & synchronous counters. Storage and shift registers.
SEQUENTIAL CIRCUITS DIGITAL design page 3 Realization of Basic Flip-flops & Simple Applications Objective : to obtain a basic understanding of FF operations. FF s are building blocks of sequential circuits and are fundamental memory devices which have two stable states: 1 (T) or 0 (F) implies that a FF can store 1 bit of info . The most basic FF is unclocked S-R Flip-flop of which are two varieties: the NOR form and the NAND form. NOR NAND state tables follow directly from truth tables of NOR and NAND gates. S R Output 0 0 0 1 1 0 1 1 No change Q = 0 Q = 1 Invalid 0 0 is the rest state S R Output 0 0 0 1 1 0 1 1 Invalid Q = 1 Q = 0 No change 1 1 is the rest state S 0 0 ? __ 1 Q R 0 2 Q 1 ? NOR S 1 1 ? 1 Q __ R 1 2 Q 0 ? NAND

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SEQUENTIAL CIRCUITS DIGITAL design page 4 S-R Flip-flops & Simple Applications S-R FF can record and store transient events. Assume that the rest state is: S = R = 0; and let Q = 0, Q = 1. At some point in time, if S while R = 0 Q = 1, Q = 0, i.e., the event ( S going high ) is recorded and stored as Q = 1. S R Output 0 0 0 1 1 0 1 1 No change Q = 0 Q = 1 Invalid 0 0 is the rest state pLH t pHL t Switching is not instantaneous i.e., propagation delays are involved S __ 1 Q R 2 Q NOR
SEQUENTIAL CIRCUITS DIGITAL design page 5 S-R Flip-flops & Simple Applications If a mechanical switch is used as an input to a digital circuit, it may cause problems – it bounces ( see Fig (a) ) before settling down. sw Switch debouncing circuit To obtain a clean signal ( see Fig (b) ) , we can use a S-R FF . Switch debouncing is a common use of S-R FF s. S R Output 0 0 0 1 1 0 1 1 No change Q = 0 Q = 1 Invalid 0 0 is the resting state Analysis: a. Vcc at OFF position: S =0, R =1 Q = 0 b. Throw switch to ON: S = , R =0 Q=1 c. Throw switch to OFF: S =0, R = Q= 0 V cc on S Q SW.DB.H _ off R Q (close) (open) ( bounce ) ( bounce ) SW (a) Undebounced switch signal (close) (open) SW.DB (b) Debounced switch signal V cc

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SEQUENTIAL CIRCUITS DIGITAL design page 6 Clock Signal : a periodic pulse train of equally spaced pulses Clock input is a controlling input to a clocked sequential circuit which specifies when FF outputs can change in response inputs.
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## This note was uploaded on 08/02/2009 for the course ECE EE2006 taught by Professor Dr.kassim during the Fall '07 term at National University of Singapore.

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DD2 - SEQUENTIAL CIRCUITS SEQUENTIAL cIRCUITS Copyright...

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