DD3 - PROGRAMMABLE LOGIC DEVICES Programmable Logic Devices...

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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 1 Programmable Logic Devices © Copyright Ashraf Kassim . All rights reserved.
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 2 Motivation for Programmable Logic Devices Complex digital circuits require many such combinational circuits requiring many such SSI/MSI components Modern circuits rarely use SSI devices to implement logic systems. x 1 x 2 f 1 (carry) x 3 f 2 (sum)
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 3 Programmable Logic Arrays Combinational circuits are realized as two-level sum of products ( SOP ), AND-OR-INVERT structures such as . Z = ABCD + ABCD + . .. Programmable array block diagram for SOP form: inputs AND product OR array terms array outputs PLD s incorporate many AND-OR-INVERT and other structures with programmable interconnections.
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 4 Programmable Logic Arrays ( PLA s) Programmable Logic Array ( PLA ): A B C fusable links AND & OR arrays are programmable AND plane produces product terms , OR plane realize sum of product terms . Commercial PLA s: come in different sizes, with many more AND and OR terms. Either mask programmed by manufacturer or user programmed ( Field Programmable PLA s – FPLAs). A A B B C C Note : n inputs implies 2 n possible product terms: A’B’C’, A’B’C, A’B C’, A’B C, A B’C’, A B’C, A B C’, A B C A’B C’ + BC ?
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 5 PLD s: Programming & Short hand notation … A PLD comes with all fuses ( ~ ) intact and the fuses are selectively blown ” during programming . The intact fuses are shown by x ’s. PLD is inserted into a programming device which is connected to a PC. User specifies logic functions to be realized on (e.g. VHDL based) software running on PC. The software generates a fuse map which specifies the fuses that are to be blown & those to be left intact to realize specified logic functions. Fuse map is downloaded to programming device , which then blows the specified fuses and tests the programmed PLD for correct operation done !
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 6 Programmable Logic Arrays ( PLA s) AND inputs are “pulled-up” high while OR inputs are “tied” low through resistors. PLD s: AND , OR inputs gate inputs are depicted as single lines : A B C +5v A B C A’B A’ B A B’ A B’ C’ C’ A’B+AB’ C’ Unwanted fuses are “Blown” Not all wires are drawn!
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PROGRAMMABLE LOGIC DEVICES DIGITAL DESIGN page 7 Programmable Read Only Memory ( PROM ) A programmable read only memory or PROM has a fully decoded AND array ( all AND terms decoded ) & a completely flexible OR array (unlike PAL ).
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DD3 - PROGRAMMABLE LOGIC DEVICES Programmable Logic Devices...

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