DD4 - DIGITAL DESIGN MODELING state Machines USING VHDL...

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DIGITAL DESIGN MODELING STATE MACHINES USING VHDL page 1 MODELING state Machines USING VHDL © Copyright Ashraf Kassim . All rights reserved.
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DIGITAL DESIGN MODELING STATE MACHINES USING VHDL page 2 State machines Modeled using case statement in a process . Branches of case contain behavior for each state. State information is stored in a signal. Triggered at rising or falling edge by: clk’event and clk='l' -- rising edge triggered clk’event and clk='0' -- falling edge triggered O R rising_edge(clk) -- function
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DIGITAL DESIGN MODELING STATE MACHINES USING VHDL page 3 Recall state machine notations name of state state NAME F CLK T state X state Y state P X A purely sequential SM is as follows: Y P
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DIGITAL DESIGN MODELING STATE MACHINES USING VHDL page 4 State machine ( SM ) notations SM with conditional branch: Decision to jump to state P or state Y is made during state X and jump occurs at next (active clock transition) ACT . Types of controller outputs: conditional unconditional : in state rectangles X Y Z F T P
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DIGITAL DESIGN MODELING STATE MACHINES USING VHDL page 5 state0 y=00 2 F id = 3H T state1 y=10 2 state2 y=11 2 F id = 7H T state3 y=10 2 T id <7H F F id = 9H T state4 y=11 2 F id = BH T State Machine m_1 based on ASM chart entity state_m_1 is port (clk, rst: in std_logic; id: in std_logic_vector(3 downto 0); y: out std_logic _vector(1 downto O)); end state_m_1; architecture archstate_m_1 of state_m_1 is type states is (state0, state1, state2, state3, state4); signal state: states; begin process (clk, rst) begin if rst='1' then state <= state0; -- asynchronous reset y < = " 0 0 " ; elsif (clk'event and clk='l') then case state is w h e n state0 => y < = " 0 0 " ; if id = x"3" then state <= state1; end if ; when state1 =>
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DD4 - DIGITAL DESIGN MODELING state Machines USING VHDL...

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