D1Intro - NATIONAL UNIVERSITY OF SINGAPORE Department of...

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NATIONAL UNIVERSITY OF SINGAPORE Department of Electrical and Computer Engineering EE2006 - Digital Design Introductory Laboratory 1 Manual Implementing and Debugging a Counter Circuit
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Objectives 1. To familiarize yourself with TTL logic IC’s and wiring digital logic circuits on a breadboard. 2. To design a free-running clock pulse generator using a 555 timer IC. Components Needed 1. 2 x 74x74 Dual D-Flip-Flops 2. 1 x 74x20 Dual Quad input NAND gate 3. 1 x 7404 Hex inverter 4. 1 x 555 Timer IC 5. 1x 7805 fixed voltage regulator 6. LED’s, Capacitors and Resistors 7. Bread board Introduction Figure 1 illustrates the schematic diagram of a 4-bit binary up-counter. The counter is designed using D flip-flops as basic building blocks. Each flip-flop has its inverted output ( Q) connected back to its own data input ( D ) causing its output to toggle for each clock pulse received on its clock (CK ) input. Four of these elements are cascaded, with the inverted output ( Q) of a previous flip-flop connected to the clock input of the next flip-flop to form a 4-bit binary up- counter. The clock input of the first (least significant bit flip-flop) is connected to an external
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This note was uploaded on 08/02/2009 for the course ECE EE2006 taught by Professor Dr.kassim during the Fall '07 term at National University of Singapore.

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D1Intro - NATIONAL UNIVERSITY OF SINGAPORE Department of...

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