EE555-USC-Spring08-Silvester-HW1

EE555-USC-Spring08-Silvester-HW1 - EE555 Broadband Network...

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EE555 – Broadband Network Architectures (Spring 2009) Homework 1: Networking Basics and Modelling Due: Tuesday January 27, 2009 Question 1. Describe the difference between datagram and virtual circuit packet switching. How is virtual circuit packet switching commonly implemented in a wide area network? Question 2. A file of length 10 Mbit is to be transmitted over a 6 (router) hop network. The (maximum) packet length is 11,000 bit (including the 1000 bit header). Each hop has a propagation delay of 3ms, processing delay (per packet) at each node is 0.1ms, there is no interfering traffic, link capacity is 1M bps. There is no circuit setup. What is the minimum time required to transmit the file? Question 3. a) What is the link utilization for the Stop-and-Wait flow control protocol (assuming no errors)? Packet length L bits, acknowledgement packets are carried in full length packets, channel capacity C bits/per second in each direction, propagation delay t (each direction), negligible packet processing time? b) The same protocol is also used for error control. If the packet error rate is p (in the forward and return channel), what is the link utilization? Question 4. What Ethernet standards (802.3) are relevant to communication over single mode fiber? What is the highest data rate Ethernet standard (IEEE) currently available for communication in a Wide Area Network? What higher speed(s) standards are under discussion and when might they become available? Question 5.
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This note was uploaded on 08/05/2009 for the course EE 555 taught by Professor Silvester during the Spring '08 term at USC.

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EE555-USC-Spring08-Silvester-HW1 - EE555 Broadband Network...

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