homework3_solution - Assigned: 3/1/05 Due: 3/10/05 CprE 211...

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Unformatted text preview: Assigned: 3/1/05 Due: 3/10/05 CprE 211 Spring 2005 Homework 3 Remember, these homework exercises not only give you practice with course concepts, but also represent the types of questions you will be tested on in an exam. I. Answer the following short questions: 1. What is the format of the CR register? There are eight fields, CR0-CR7. Each CR field has four bits: 0 LT, 1 GT, 2 EQ, 3 SO. 2. What are the exception bits in the XER register? SO Summary overflow OV Overflow CA Carray 3. What is the use of the LR register? LR is Link Register. 1. Provide the branch target address for a branch instruction that uses LR as the target address. 2. Hold the address of instruction that follows a branch and link instruction. 4. [2] Using PowerPC assembly instructions, write code to store the integer value 0x23000034 (4-byte) into memory at address 0x200055C0. Notes: To use store instruction, the value to be stored must be saved in a register. To use a 32-bit address, the upper half of the address must be put into a register. Thus, let r3 hold 0x23000034 and r4 hold the address. lis r3, $2300 ori r3, $0034 lis r4, $2000 stw r3, $55C0(r4) 5. The instruction lis is a pseudo instruction. How is it translated to a native PowerPC instruction? lis rA, value addis rA, 0, value 1 Assigned: 3/1/05 Due: 3/10/05 II. Consider the following memory dump and PowerPC registers. Assume that byte-ordering is big endian (big byte first, i.e., MSB at lower address) and memory addresses are 32 bits wide. Address 30001FF8 30002000 30002008 30002010 ... 30FF0000 30FF0008 30FF0010 30FF0018 25 00 AC 01 30 AC 30 30 Memory Contents 24 5B 1A AC 57 9C FE 25 24 5B 1A EE AE 81 83 45 67 89 23 55 3F AC CB F0 00 AE 00 FF FF 81 50 00 18 83 04 50 20 30 AC 20 00 00 CB 00 10 32 F0 10 8D 05 25 8D 8C 00 8D A8 Register R1 R20 R21 R22 R23 R24 R25 R26 LR CR XER Register Contents 30FF0000 2000FF10 00008000 FFF00100 30002008 0FFF9001 30002000 30FF0018 200011A0 unknown unknown Answer the following questions. "What is the result" means what registers and/or memory locations are affected and what are their values. The registers include CR and XER. Each instruction is independent. SP is an alias of R1. 1. What is the result of the instruction: addo. r24, r24, r21 "o" to set XER[OV] and XER[SO] bits. "." to set CR0[LT], CR0[GT], CR0[EQ], and CR0[SO] bits. Sources: R24 = $0FFF9001, r21=$00008000, R24 = $10001001 XER[OV] = 0, XER[SO] unchanged CR0[LT] = 0, CR0[GT] = 1, CR0[EQ] = 0; CR0[SO] = XER[SO]. 2. What is the result of the instruction: addc "c" to set XER[CA] Sources: r22 = FFF00100, r23 = 30002008 r20 = 0x2FF02108 XER[CA] = 1; r20, r22, r23 3. What is the result of the instruction: addic. r20, r22, 0x8000 "c" to set XER[CA] "." to set CR0[LT], CR0[GT], CR0[EQ], and CR0[SO] bits. r20 = FFF00100+$8000 = FFF08100 XER[CA] = 0, CR0[LT] = 1, CR0[GT] = 0, CR0[EQ] = 0. 4. What is the result of the instruction: addis r20, r21, 0 Addis add immediate shifted R20 = $00008000 + 0 << 16 = $00008000 2 Assigned: 3/1/05 Due: 3/10/05 5. [1] What is the result of the instruction: stwu r26, -24(r26) "u" update, in this case update r26 with the EA (effective address) -24 = -$18, thus EA = -24(r26) = $30FF0000. Memory write 30FF0000 30 00 FF 18 20 00 10 8C R26 = $30FF0000 6. What is the result of the instruction: lmw r28, 8(sp) Lmw load multiple word starting from the EA. EA = 8(SP) = $30FF0008. R28 = $ACAE8183, R29 = $30003200 R30 = $30005004, R31 = $ACCBF08D 7. What is the result of the instruction: Mflr move from LR. R20 = (LR) = 200011A0 mflr r20 8. Suppose that the program control is within the code of a function generated by an EABIcompatible compiler. What is the frame size of the function? What is the return address? According to EABI stack frame format, 0(SP) stores the back chain (the stack top of the caller). SP = $30FF0000, 0(SP) is $30FF0018, thus the frame size is the difference $18 or 24. 3 Assigned: 3/1/05 Due: 3/10/05 III. Given the following information and PowerPC assembly program fragment, fill in the blanks. Register r1 (SP) r3 r5 r8 r10 Program Fragment addi r3,r3,4 bl func1 b end func1: mflr r8 stwu SP, -8(SP) stw r8, 4(SP) bl func2 stw r3, 0(r5) lwz r8, 4(SP) mtlr r8 addi SP, SP, 8 blr func2: stw r3,0(r10) addi r3,r3,1 blr Initial Value 0x00008000 0x00000000 0x00003000 0x00000000 0x000FFFFF After the instruction executes: LR 0x00005000 (return address) r8 = ____0x00005000__ SP = ____0x00007FF8 SP = ____0x00007FF8_ r5 = ____0x00003000__ r8 = ____0x00005000__ LR = ____0x00005000__ SP = ____0x00008000__ M[SP] = ____0x00008000_ M[SP+4] = ____0x00005000_ M[r5+0] = ____0x00000005 end: 4 Assigned: 3/1/05 Due: 3/10/05 IV. Consider the following C program: C Code //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////// // short MaxOfNibbles(char *arr, short numElements) // description: // Returns a short value that is the maximum of the lower nibble //values in the array for array elements in which bit 7 is set to 1 // // params: // char *arr: char array in which to find the maximum lower nibbles // short numElements: number of elements in the char array // // returns: // returns the maximum of lower nibble values for which bit 7 = 1 char MaxOfNibbles(char arr , short numElements) { //short var to store the summation of lower nibble values char maxLowNib = 0; int i; // walk through the array, find the maximum nibble value // in the array for elements having bit 7 = 1 for (i=0; i<numElements; i++) { // if bit 7 of arr[I] is 1, add the lower nibble of // arr[i] to sumLowNib if (arr[i]&0x80) == 0x80 && arr[i]>maxLowNib) maxLowNib = arr[i]&0x0F; } return maxLowNib; } 5 Assigned: 3/1/05 Due: 3/10/05 The following assembly code is incomplete: non-branch instructions lack operands. ; ; ; ; ; ; ; ; ; THIS CODE IS INCOMPLETE: give Parameters are passed in r3 Result is returned in r3 register usage: r31 maxLowNib r30 i r29 arr[i] r28 tmp value for arr[i] r27 tmp value for arr[i] missing operands for each inst arr, r4 numElements & 0x80 & 0x0F MaxOfNibbles: ; Initialize local variables li r31,0 ; maxLowNib = 0 li r30,0 ; i = 0 ; Start for loop, loop from i = 0 till numElements ForLoop: ; Load in value from arr[i] lbzx r29, r3, r30 ; bitwise AND arr[i] with 0x80 andi r28,r29, $80 ; compare to see if equal to 0x80 cmpwi r28, $80 ; if !(arr[i] & 0x80 != 0x80) then skip comparing lower nibble bne SkipCompare ; compare arr[i] and maxLowNib cmpwi r29, r31 ; if !(arr[i]>maxLowNib) then skip assignment ble SkipChange ; calculate arr[i]&0x0F andi r27, r29, $0F ; maxLowNib = arr[i]&0x0F 6 Assigned: 3/1/05 Due: 3/10/05 mr r31, r27 SkipCompare: ; Increment for loop counter (i++) addi r30,r30, 1 ; Compare i with numElements cmpw r30, r4 ; if i < numElements then continue for loop, else drop out blt ForLoop Done: ; move maxLowNib to the register used for the return value mr r3, r31 1. Complete the above assembly program. 2. Write the prologue code for the function (use the EABI modifications). You should minimize the number of instructions. Use the following stack frame format: Higher addresses 36(sp) 32 28 24 20 16 12 8 4 0(sp) Caller Stack Frame Callee Saved LR Caller Frame Header R31 R30 R29 R28 R27 Padding LR Saved Word Back chain word // Prologue addi sp, sp, -32 ; allocate stack frame space mflr r0 ; get LR stw r0, 36(sp) ;save LR stmw r27, 12(sp) ;save bank of NVS starting with r27 7 Assigned: 3/1/05 Due: 3/10/05 3. Write the epilogue code for the function (use the EABI modifications). You should minimize the number of instructions. // Epilogue lmw r27, 12(sp) lmz r0, 36(sp) mtlr r0 addi sp, sp, 32 blr ;restore bank of NVS starting with r27 ;get the saved LR ;restore LR ;deallocate stack frame space ; exit and return to caller using LR 8 ...
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This note was uploaded on 04/02/2008 for the course CPR E 211 taught by Professor Wang during the Spring '06 term at Iowa State.

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