homework 5 solution

homework 5 solution - Assigned: 4/13/05 Completed by:...

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Unformatted text preview: Assigned: 4/13/05 Completed by: 4/20/05 CprE 211 Spring 2005 Homework 5 Solution Last Name First Name Section _________________________ _________________________ _____________________ Grading Procedure for Homework: This homework will not be collected and not be graded. The solution will be distributed on-line one week later. Remember, these homework exercises not only give you practice with course concepts, but also represent the types of questions you will be tested on in an exam. 1 Assigned: 4/13/05 Completed by: 4/20/05 I. Interrupt ESR and Interrupt Service Routines (ISRs) a. The following is a code snippet from an implementation of Interrupt ESR. What does the code do? Explain each instruction. Create a stack frame, and save r3 and machine context SRR0 and SRR1 into the frame, and then save SRR0 and SRR1 into the stack. Register r3 is used as a bridge in saving SRR0 and SRR1. It must be saved first because it is changed. stwu sp, -40 (sp) ; create a frame of 40 bytes stw r3, 24 (sp) ; save r3 to stack mfsrr0 r3 ; move SRR0 to r3 stw r3, 12 (sp) ; save it to stack mfsrr1 r3 ; move SRR1 to r3 stw r3, 16 (sp) ; save it to stack (Note: This question was given in HW4.) b. Consider the code in (a) again. If another interrupt is raised when the processor is executing "stw r3, 24 (sp)," and the interrupt is not masked and not disabled, what would happen to the execution of "mfsrr0 r3"? Assume no other interrupt occurs. When executing "stw r3, 24(sp)", the next PC points to "stw r3, 24(sp)", and MSR has been changed during by hardware. If another interrupt would be allowed to be raised, SRR0 and SRR1 would be overwritten. The next PC and MSR content of the original execution would be lost, and the program control could not be returned there. c. TRUE or FALSE "mtspr EIE, r3" and "mtspr EIE, r5" are equivalent in execution. TRUE. The effect of assigning a value to EIE is set MSR[EE] and MSR[RI] bits. No bits of the source register are really used. d. What does the following code do? .equ .equ lis ori A_SIUBase 0x002F A_SIUOffset 0xC000 r31,A_SIUBase r31,r31,A_SIUOffset Initializes r31 to the base address of a set of memory-mapped registers on the MPC555 used for the System Interface Unit, which includes selected on-chip I/O devices and the interrupt controller. r31 0x002FC000 2 Assigned: 4/13/05 Completed by: 4/20/05 e. Given the code in part d. that sets up r31, what does the following code do? Be specific, and give your answer in terms related to the operation of the PIT. A_PISCR .equ 0x0240 li r0,0x4085 sth r0,A_PISCR(r31) The value 0x4085 is written to the PIT Status and Control Register (PISCR) at address r31+0x0240=0x002FC240. Interrupt request field = 0x40, assigning Level 1 interrupt. With 0x8, PS status flag is written with 1, thus clearing it. With 0x5, the PIE and PTE bits are set, enabling interrupts and the timer. f. Given the code in part f. for r31, fill in the blank in the code below to enable the Level 1 interrupt, leaving all other mask bits unchanged. A_SIMASK lhz ori sth .equ 0x0014 r0, A_SIMASK(r31) r0, r0, 0x1000_ r0, A_SIMASK(r31) g. Given the code in part f. for r31, and the code below, answer the questions. A_SIVEC lbz li addis add lwz .equ 0x001C r0,A_SIVEC(r31) r30,InterruptTable@l r30,r30,InterruptTable@h r30,r30,r0 r2,0(r30) .data InterruptTable: .long InterruptHandlerIRQ0 .long InterruptHandler0 .long InterruptHandlerIRQ1 .long InterruptHandler1 .long InterruptHandlerIRQ2 .long InterruptHandler2 .long InterruptHandlerIRQ3 .long InterruptHandler3 .long InterruptHandlerIRQ4 .long InterruptHandler4 .long InterruptHandlerIRQ5 .long InterruptHandler5 .long InterruptHandlerIRQ6 .long InterruptHandler6 .long InterruptHandlerIRQ7 .long InterruptHandler7 3 Assigned: 4/13/05 Completed by: 4/20/05 (a) What is the value in r0 for a Level 1 interrupt (at the end of the code segment)? 0x0000000C (b) Let InterruptTable = 0x40000100. What is the value in r30 (at the end of the code segment)? The address of the table entry in InterruptTable corresponding to the ISR to be called r30+r0 = 0x40000100+0x0000000C = 0x4000010C (c) What gets loaded into register r2 for a Level 1 interrupt? The word in memory at 0(r30), i.e., M[0x4000010C], which is the entry in the interrupt vector (jump) table for InterruptHandler1 the value in the data section for InterruptHandler1, i.e., .long InterruptHandler1 in which InterruptHandler1 is the address of the ISR for Level 1 interrupt r2 the 32-bit value of the label InterruptHandler1 II. PIT Programming 1. Refer to the InitTimer C subroutine below. Notice the steps identified in InitTimer, STEP 1 STEP 5. Each step corresponds to an operation in the Interrupt System. There are three places, A C, in the Interrupt System where these operations occur. Put each number (1-5) in a blank (A-C) corresponding to where that numbered step takes place. You will use all the numbers, so more than one number may be written in a blank. A I/O Device: B Interrupt Controller: C PowerPC CPU: _____1, 2, 3_______ ________4________ ________5________ void InitTimer () { // STEP 1: MODULE SPECIFIC INITIALIZATION USIU.PITC.B.PITC = 0xF423; // Set count value USIU.PISCR.B.PTE = 1; // PIT enabled to start counting // STEP 2: LEVEL ASSIGNMENT USIU.PISCR.B.PIRQ = 0x02; // Level 6 PIT interrupt 4 Assigned: 4/13/05 Completed by: 4/20/05 // STEP 3: ENABLE INTERRUPT USIU.PISCR.B.PIE = 1; // Enable PIT interrupt // STEP 4: SET APPROPRIATE SIMASK BITS USIU.SIMASK.R = 0x00040000; // Enable level 6; others disabled // STEP 5: SET MSR[EE], MSR[RI] BITS asm("mtspr EIE, r0"); } 2. Suppose you are monitoring the position of a valve in a flow unit of a chemical processing plant. Write the C code to sample the position at a rate of 60 times a second. Your task is to initialize the PIT timer subsystem and to write the ISR. Both subroutines should be written in C. Assume a main program calls your initialization/setup routine. Assume an exception handler has been written and calls your ISR using an interrupt vector table. Thus, you need to write C code for the following two functions: // Initialization void Init_Valve_Monitor () - Initialize the PIT appropriately; let level assignment be 5 // Interrupt Service Routine void ISR_Valve_Monitor () - Service the interrupt appropriately - If a sample should be taken, call the function given by the prototype void Read_Valve_Position (); Assumptions: - PIT period: Pre-divider value of 4 with a 20 MHz clock - The Read_Valve_Position function is already written; all you need to do is to call it in your function. - Someone else will write the main program to call Init_Valve_Monitor (no need to write main). - Someone else will write the exception handler to call ISR_Valve_Monitor (no need to write the exception handler). 5 Assigned: 4/13/05 Completed by: 4/20/05 Solution: Refer to the information on the MPC555 interrupt system. The level assignments are listed in a table, where Level 5 = 0x04. In SIMASK, Level 5 is bit 11 (MSB is bit 0). Recall that a final step in initialization is enabling the CPU to see the interrupt by setting the MSR[EE] bit. After any interrupt sources have been initialized, the enable external interrupts [EE] bit must be set for interrupts to be recognized (in addition, the recoverable interrupt [RI] bit is set to tell exceptions the state is recoverable). This is done by using the EIE special purpose register. Writing any value to the EIE register sets both the MSR[EE] and MSR[RI] bits. Writing is accomplished by using the mstpr instruction. Example: mtspr EIE, r0 The initialization function should do the following: assign an initial count value to PITC assign the interrupt level in PISCR clear the PIT status flag enable interrupts using PIE, SIMASK, and EE, and enable the timer using PTE To sample at 60 times per second, the delay between samples is 1/60th second or 0.0167 s = 16.7 ms. The maximum delay for the PIT period given the timing parameters is: PIT period = (PITC + 1) / (clockfreq / prediv) = (0xFFFF + 1) / (20M / 4) = 65536 / 5M = 0.0131 s = 13.1 ms Thus, the delay between samples exceeds the maximum delay of one PIT period. More than one PIT period will be needed. Let's set up the PIT period as half the sample period and sample every 2 PIT periods. PIT period = 8.33 ms = (PITC + 1) / 5M PITC = (8.33 m (5M) ) 1 = 41665.7 41665 = A2C1 6 Assigned: 4/13/05 Completed by: 4/20/05 Two coding examples for Init_Valve_Monitor are shown. void Init_Valve_Monitor() { short *pPISCR = (short *) 0x002FC240; short *pPITC = (short *) 0x002FC244; short *pSIMASK= (short *) 0x002FC014; short nPISCR; short nSIMASK; // assign an initial count value to PITC *pPITC = 0xA2C1; // enable interrupts in interrupt controller and CPU nSIMASK = *pSIMASK; // Read the SIMASK nSIMASK = nSIMASK | 0x0010; // set Level 5 bit *pSIMASK = nSIMASK;// leave other bits unchanged asm("mtspr EIE, r0"); // set the EE bit // assign interrupt level (0x04--), clear PS (0x--8-), // set PTE, set PIE (0x---5) in PISCR *pPISCR = 0x0485; } void Init_Valve_Monitor() { typedef unsigned char UINT8; typedef unsigned short UINT16; typedef unsigned long UINT32; struct USIU_tag { union { UINT16 R; struct { UINT16 PIRQ:8; UINT16 PS:1; UINT16:4; UINT16 PIE:1; UINT16 PITF:1; UINT16 PTE:1; } B; } PISCR; union { UINT32 R; struct { UINT32 PITC:16; UINT32:16; } B; 7 Assigned: 4/13/05 Completed by: 4/20/05 } PITC; }; struct USIU_tag USIU; // see Note at end of this answer // STEP 1: MODULE SPECIFIC INITIALIZATION USIU.PITC.B.PS = 1; // Clear the status flag by writing a 1 USIU.PITC.B.PITC = 0xA2C1; // Set up count value USIU.PISCR.B.PTE = 1; // PIT enabled to start counting // STEP 2: LEVEL ASSIGNMENT USIU.PISCR.B.PIRQ = 0x04; // Level 5 PIT interrupt // STEP 3: ENABLE INTERRUPT USIU.PISCR.B.PIE = 1 ; // Enable PIT interrupt // STEP 4: SET APPROPRIATE SIMASK BITS USIU.SIMASK.R = 0x00100000; // Enable level 5 only // FINAL STEP: SET MSR[EE], MSR[RI] BITS asm("mtspr EIE, r0"); } //global variable char sample_period = 0; void ISR_Valve_Monitor () { short *pPISCR = (short *) 0x002FC240; short nPISCR; // read the position every other PIT period if (sample_period == 1) { Read_Valve_Position (); sample_period = 0; } else sample_period = 1; nPISCR = *pPISCR; // clear the PS flag nPISCR = nPISCR | 0x0080; *pPISCR = nPISCR; } NOTE: The method to assign address 0x2FC000 to USIU for the CodeWarrior environment in the lab must be determined. The MPC555 header file was found at: e-www.Motorola.com/collateral/M555HEADER.zip 8 Assigned: 4/13/05 Completed by: 4/20/05 (Microcontrollers Products 32-bit MPC500 MPC555 Tools Software Code Examples) /******************************************************************/ /* There are three way to create an instance of the USIU module: */ /* -Use a fixed structure (Default) */ /* -Use the Diab compiler sections (if DIAB_SCETIONS is defined) */ /* -Use a pointer (if HEADER_POINTERS is defined) */ /******************************************************************/ #ifdef DIAB_SECTIONS /* Diab Compiler Only */ #pragma section USIU address=0x2FC000 /* Map modules to fixed addresses. */ #pragma use_section USIU USIU EXT struct USIU_tag USIU; #else #ifdef HEADER_POINTERS /* Create a global pointer. */ #ifdef Main_Program struct USIU_tag *USIU = (struct USIU_tag *) (INTERNAL_MEMORY_BASE + 0x2FC000); #else EXT struct USIU_tag *USIU; #endif #else /* Use a fixed structure, this is the default */ #define USIU (*( struct USIU_tag *) (INTERNAL_MEMORY_BASE + 0x2FC000)) #endif /* HEADER_POINTERS */ #endif /* DIAB_SECTIONS */ 9 Assigned: 4/13/05 Completed by: 4/20/05 III. ADC Basics 1. Suppose an ADC subsystem monitors the gas pressure exerted on a valve. A sensor circuit reads the pressure and outputs a proportional voltage. The pressure has a range of 10 psi to 150 psi. The ADC unit for this question is an 8-bit ADC with a range of 2V to 10V. Note that this ADC is different than the QADC of the MPC555. Let AV be Analog Value; DN be Digital Number: AV = DN * Step Size + Offset DN = (AV - Offset) / Step Size i. Offset Span Step Size Complete the calculations below (list the results as decimal values): Pressure Voltage into ADC on Analog Input 10 psi 150-10 = 140 psi 140/256 = 0.547 psi 2V 10-2 = 8 V 8/256 = 0.03125 V ii. Suppose the Gas Pressure is 74.9 psi. Convert to digital, giving your answer in hex (approximate the decimal value). DN = (AV - Offset) / Step Size (74.9-10) / 0.547 = 118.6 118 = 0x76 iii. Suppose that the ADC uses the Successive Approximation method. For an input voltage of 9V, what is the value of the Most Significant Bit of the digital number? Work out the following table to show the steps of the method (as did in the class). The first step is given. Step 0 1 2 3 4 5 6 7 Range xxxxxxxx 1xxxxxxx 11xxxxxx 111xxxxx 1110xxxx 11100xxx 111000xx 1110000x DN_Mid 10000000 11000000 11100000 11110000 11101000 11100100 11100010 11100001 AV_Mid(V) Input >= AV_Mid 6.0 (corrected) 1 (yes) 8.0 1 (yes) 9.0 1 (yes) 9.5 0 (no) 9.25 0 (no) 9.125 0 (no) 9.0625 0 (no) 9.03125 0 (no) Answer: 11100000 10 Assigned: 4/13/05 Completed by: 4/20/05 2. Compute the memory needed in bytes to store a 4-bit digital encoding of a 3-second analog audio signal sampled every 10 milliseconds. 3 s / 10 ms per sample = 300 samples 300 samples X 4 bits per sample = 1200 bits = 150 bytes 11 Assigned: 4/13/05 Completed by: 4/20/05 MPC555 Registers PIT Module Interrupt Controller 12 Assigned: 4/13/05 Completed by: 4/20/05 13 Assigned: 4/13/05 Completed by: 4/20/05 CPU Register Machine State Register: EE bit bit 16 (where bit 0 = MSb) For value = 0xA042: EE bit =1 (processor is enabled to take an external interrupt) FP bit = 1 (processor can execute floating-point instructions) IP bit = 1 (exception vector table starts at address 0xFFF00000) RI bit = 1 (machine state is recoverable) LE bit = 0 (processor operates in big-endian mode) Inline assembly instruction to set the EE and RI bits: asm("mtspr EIE, r0"); 14 ...
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