homework4_solution

homework4_solution - Assigned: 3/23/05 Due: 3/29/05 CprE...

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Unformatted text preview: Assigned: 3/23/05 Due: 3/29/05 CprE 211 Spring 2005 Homework 4 Solution Remember, these homework exercises not only give you practice with course concepts, but also represent the types of questions you will be tested on in an exam. I. C control statements translation 1. The general form of an if-else statement in C is given by the template: if (test-expr) then-statement else else-statement where test-expr is an integer expression that evaluates either to 0 (interpreted as meaning false) or to a nonzero value (interpreted as meaning true). Only one of the two branch statements is executed. The translation to assembly code may adhere to the following form, where C syntax describes the control flow. t = test-expr; if (!t) goto false; then-statement goto done; flase: else-statement done: // conditional branch // unconditional branch That is, the compiler generates separate blocks of code for then-statement and else-statement. It inserts conditional and unconditional branches to make sure the correct block is executed. In the PowerPC architecture, "t = test-expr" is not always needed. Consider the following example. The left side is a conventional C program. The right side is its goto version. if (x > y) max = x; else max = y; if (x <= y) goto false; max = x; goto done; false: max = y; done: 1 Assigned: 3/23/05 Due: 3/29/05 The goto version can be translated into assembly as follows. Suppose that x is bound to r3, y to r4, and max to r5. cmpw r3, r4 ble false mr r5, r3 goto done false: mr r5, r4 done: Given the C code below, write a goto version in C that performs the same computation, and then write a version in PowerPC assembly. Note: You can use registers as you wish as long as you avoid dedicate registers in EABI. Assume all variables are not in registers initially (so you need to use load/store instructions). And in PowerPC assembly you can use "var@h" and "var@l" to specify the higher and lower halves of the address of symbol var, e.g. "lw r4, var@h(r3)". int sum; int missed; int *p_data; ... if (p_data != NULL) sum += *p_data; else missed ++; ... ; compare x and y ; branch to false if x<=y ; max = x ; skip the else part ; max = y Goto version (without declarations): if (p_data == NULL) goto false; sum += *p_data; goto done; false: missed++; done: 2 Assigned: 3/23/05 Due: 3/29/05 Assembly version: Assume variables are bound to memory locations, and they must be loaded from and stored back to memory. ; Register Use ; r0 tmp variable ; r3 p_data ; r4 *p_data ; r5 sum ; r6 missed ; if (p_data == NULL) goto false; lis r0, p_data@h lwz r3, p_data@l(r0) cmpi r3, 0 beq false ; condition true: sum += *p_data; goto done; lwz r4, 0(r3) ; load *p_data lis r0, sum@h lwz r5, sum@l(r0) add r5, r5, r4 stw r5, sum@l(r0) b done false: ; condition false: missed++; lis r0, missed@h lwz r6, missed@l(r0) addi r6, r6, 1 sth r6, missed@l(r0) done: 3 Assigned: 3/23/05 Due: 3/29/05 2. Consider the different types of loops in C. The general form of a do-while statement is: do body-statement while (test-expr); The goto implementation of do-while is: loop: body-statement t = test-expr; if (t) goto loop; // conditional branch The general form of a while statement is: while (test-expr) body-statement goto version of while: loop: t = test-expr; if (!t) goto done; // conditional branch body-statement goto loop; // unconditional branch done: Alternatively, here is a goto version with only one branch inside the loop: goto test; // conditional branch loop: body-statement test: t = test-expr; if (t) goto loop; // conditional branch done: Finally, the general form of a for statement is: for (init-expr; test-expr; update-expr) body-statement This is identical to the following while loop: init-expr; while (test-expr) { body-statement update-expr; } 4 Assigned: 3/23/05 Due: 3/29/05 Thus, the goto version for a for statement is derived from the goto version of a while statement. Given the C code below, write a goto version in C that performs the same computation, and then write a version in PowerPC assembly. unsigned char byArray[10]; char checksum = 0; int i; for (i=0; i<10; i++) { if (byArray[i] & 0x80) checksum ^= byArray[i]; } Goto version (without declaration): The Goto-version for generic if statement using a single branch inside the loop: init-expr; goto test; // conditional branch loop: body-statement update-expr; test: t = test-expr; if (t) goto loop; // conditional branch done: Goto version for the code above: checksum = 0; i = 0; goto test; loop: t0 = byArray[i] & 0x80; if (t0 == 0) goto false; checksum ^= byArray[i]; false: i++; test: if (i < 10) goto loop; done: 5 Assigned: 3/23/05 Due: 3/29/05 Assembly version: ; ; ; ; ; ; ; register usage: r0 tmp r31 byArray r30 checksum r3 i r4 byArray[i] r5 t0 ; first, set up byArray ; checksum = 0 ; i = 0 ; goto test ; ; ; ; ; load byArray[i] t0 = byArray[i] & 0x80 if (t0 == 0)? equal: goto false checksum ^= byArray[i]; lis r31, byArray@h ori r31, byArray@l li r30, 0 li r3, 0 b test loop: lbzx r4, r31, r3 andi r5, r4, $80 cmpwi r5, 0 beq false xor r30, r30, r4 false: addi r3, r3, 1 test: cmpwi r3, 10 blt loop done: ; i++ ; if (i < 10)? ; less than: goto loop 6 Assigned: 3/23/05 Due: 3/29/05 II. I/O Subsystems and Interrupts Refer as needed to the information about the MPC555 Interrupt System at the end of this packet. a. Think about how an external interrupt request makes its way from an I/O device to the CPU. Order the following actions by placing a number in each blank, starting with 1 for what happens first, 2 for what happens next, etc. Order (1-9) 5 or 6 3 9 2 or 1 6 or 5 4 8 1 or 2 7 Action Interrupt vector register (SIVEC) indicates the highest priority unmasked interrupt level Device asserts an interrupt request signal CPU executes rfi instruction Programmer sets the device interrupt enable bit CPU receives an external interrupt request Interrupt pending register (SIPEND) indicates an interrupt at one or more levels CPU executes Interrupt Service Routine for level Programmer sets the interrupt mask bit (in SIMASK) corresponding to the level of the device CPU executes Exception Handler for external interrupt b. TRUE or FALSE: One difference between polling-based I/O and interrupt-driven I/O is that only polling uses a ready flag in the device's status register. FALSE. ISR should also check the device status register. 7 Assigned: 3/23/05 Due: 3/29/05 c. What are SIVEC, SIPEND and SIMASK registers? What is the UIPEND register? How does software (e.g. an exception service routine) access those registers? SIVEC is SIU interrupt vector register, located at USIU. (SIU is System Interface Unit). It is an 8-bit code representing the unmasked interrupt source of the highest priority level. (Only 4 bits are significant because the USIU interrupt controller recognizes 16 interrupt requests.) SIPEND is SIU interrupt pending register, located at USIU. Each bit in the SIPEND register corresponds to an interrupt request. UIPEND is a register at UIMB which reflects the state of the 32 UIMB interrupt levels. SIVEC, SIPEND and UIPEND are memory-mapped. At the machine level, software uses load/store instructions to read or write those registers. d. What are registers MSR, SRR0, and SRR1? What are their uses? MSR is machine state register. It defines the state of the processor, e.g. whether the execution is interruptible (the EE bit), whether exception is recoverable (the RI bit), at what privilege level the processor is running (the PR bit), and many others. SRR0 and SRR1 are Machine Status Save/Restore Registers. When an exception happens, the processor saves PC to SRR0 and selected MSR bits to SRR1. Note: The processor must save PC and MSR, because they are changed before the program control is transferred to the ESR. e. Suppose that an on-chip I/O device is programmed to use interrupt level 3, and it raises an interrupt. Which bit of SIPEND is set? What is the value of SIVEC? Assume there is no other interrupt request and SIMASK bits are all set. Bit 7. The formula is 2k+1, where k is the interrupt level. (See also the layout of SIPEND bits). SIVEC = 28 or 0x1C. The formula is 4*(2k+1). (See also the SIVEC code table.) f. Suppose that an external I/O device is connected to IRQ pin 5, and it raises an interrupt. Answer the questions in (e) again. Bit 10. The formula is 2k, where k is the IRQ pin number. (See also the layout of SIPEND bits). SIVEC = 40 or 0x28. The formula is 4*(2k). (See also the SIVEC code table.) 8 Assigned: 3/23/05 Due: 3/29/05 g. Suppose that the I/O devices in (e) and (f) are used together (connected to the same level and pin, respectively). If they raise interrupts simultaneously, what is the value of SIPEND? What is the value of SIVEC? Assume there is no other interrupt request and SIMASK bits are all set. Bits 7 and 10 are both set, and other bits are clear. SIVEC = 28, because the priority of interrupt level 3 is higher than that of IRQ pin 5. h. Consider (g) again. Support at a point the software needs to disable interrupt from the external I/O devices, which is connected to IRQ pin 5. What value should be written into SIMASK? Does that affect the value in SIPEND? IRQ pin 5 corresponds to bit 10 of SIMASK. The upper half of SIMASK should be set to b'1111 1111 1101 1111 or 0xFFDF. NOTE: The PowerPC manual uses Big-endian Bit Ordering, with which bit 0 is the most significant (leftmost) bit. i. What does the following code do? Give comment to each instruction. Determine the address of the ISR corresponding to the current SIVEC code. First the SIVEC code is read. Then the ISR address is read from the corresponding table entry, and then a function call is made to the ISR address. .equ SIVEC 0x2FC01C ; memory port for SIVEC lis r3, SIVEC@h ; load SIVEC base addr lbz r3, SIVEC@l(r3) ; load SIVEC code lis r4, Interrupt_Table@H ; set up ISR table addr ori r4, r4, Interrupt_Table@L ; set up ISR table addr lwzx r4, r4, r3 ; load ISR addr mtlr r4 ; move the addr to LR blrl ; function call using LR j. What does the following code do? Give comment to each instruction. Create a stack frame, and save r3 and machine context SRR0 and SRR1 into the frame, and then save SRR0 and SRR1 into the stack. Register r3 is used as a bridge in saving SRR0 and SRR1. It must be saved first because it is changed. stwu sp, -40 (sp) stw r3, 24 (sp) mfsrr0 r3 stw r3, 12 (sp) mfsrr1 r3 stw r3, 16 (sp) ; ; save ; ; save ; ; save create a frame of 40 bytes r3 to stack move SRR0 to r3 it to stack move SRR1 to r3 it to stack 9 Assigned: 3/23/05 Due: 3/29/05 (1) Interrupt Controller 10 Assigned: 3/23/05 Due: 3/29/05 Interrupt Vector Identification by Exception Handler Interrupt Source 0 Level 0 1 Level 1 2 Level 2 3 Level 3 4 Level 4 5 Level 5 6 Level 6 7 Level 7 Priority 0 (highest) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (lowest) Binary Value 00000000 00000100 00001000 00001100 00010000 00010100 00011000 00011100 00100000 00100100 00101000 00101100 00110000 00110100 00111000 00111100 Hex Value 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 11 Assigned: 3/23/05 Due: 3/29/05 CPU Register Machine State Register: EE bit bit 16 (where bit 0 = MSb) For value = 0xA042: EE bit =1 (processor is enabled to take an external interrupt) FP bit = 1 (processor can execute floating-point instructions) IP bit = 1 (exception vector table starts at address 0xFFF00000) RI bit = 1 (machine state is recoverable) LE bit = 0 (processor operates in big-endian mode) Inline assembly instruction to set the EE and RI bits: 12 Assigned: 3/23/05 asm("mtspr EIE, r0"); Due: 3/29/05 13 ...
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