UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Dept. of Electrical Engineering and Computer Sciences EECS 40 Fall 2003 Homework Assignment #12 Due at 11:00 AM in 240 Cory on Monday, 12/5/03 * Be sure to put your Discussion Section number on your paper; otherwise 5 pts will deducted from your score! Problem 1: Interconnect Delay Consider the cascaded CMOS inverters below: ABVoutVininterconnectWe are interested in the propagation delay of Inverter A (between Vinand Vout). The equivalent on-resistance Rdrof the NMOSFET or PMOSFET in Inverter A is 10 kΩ. The intrinsic capacitance Cintrinsic(due to the drain pn-junction capacitances and gate-overlap capacitances for Inverter A) is 3 fF; the fanout capacitance Cfanout(input capacitance of Inverter B, i.e.the MOSFET gate capacitances for Inverter B) is 3 fF. Suppose the oxide (SiO2, with dielectric permittivity εSiO2= 3.45×10-13F/cm) between the aluminum (resistivity = 2.7 µΩ-cm) metal layer and the silicon substrate is 1 µm thick (i.e.tdi= 1 µm).
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This note was uploaded on 08/08/2009 for the course ECE 210 taught by Professor Whoever during the Fall '07 term at University of Illinois at Urbana–Champaign.