80c32(Themic) - 80C32/80C52 Rev. G (14 Jan. 97) 1 MATRA MHS...

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Unformatted text preview: 80C32/80C52 Rev. G (14 Jan. 97) 1 MATRA MHS Description TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit μ C. The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C52 retains all the features of the 8052 : 8 K bytes of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit timers ; a 6-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. In addition, the 80C52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 80C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with Vcc = 5 V. TEMIC’s 80C52 and 80C32 are also available at 16 MHz with 2.7 V < V CC < 5.5 V. D 80C32 : Romless version of the 80C52 D 80C32/80C52-L16 : Low power version Vcc : 2.7 – 5.5 V Freq : 0-16 MHz D 80C32/80C52-12 : 0 to 12 MHz D 80C32/80C52-16 : 0 to 16 MHz D 80C32/80C52-20 : 0 to 20 MHz D 80C32/80C52-25 : 0 to 25 MHz D 80C32/80C52-30 : 0 to 30 MHz D 80C32/80C52-36 : 0 to 36 MHz D 80C32-40 : 0 to 40 MHz* D 80C32-42 : 0 to 42 MHz* D 80C32-44 : 0 to 44 MHz* * 0 to 70 ° C temperature range. For other speed and temperature range availability please consult your sales office. Features D Power control modes D 256 bytes of RAM D 8 Kbytes of ROM (80C52) D 32 programmable I/O lines D Three 16 bit timer/counters D 64 K program memory space D 64 K data memory space D Fully static design D 0.8 μ CMOS process D Boolean processor D 6 interrupt sources D Programmable serial port D Temperature range : commercial, industrial, automotive, military Optional D Secret ROM : Encryption D Secret TAG : Identification number CMOS 0 to 44 MHz Single Chip 8–bit Microntroller 80C32/80C52 Rev. G (14 Jan. 97) 2 MATRA MHS Interface Figure 1. Block Diagram 80C32/80C52 Rev. G (14 Jan. 97) 3 MATRA MHS Figure 2. Pin Configuration 80C32/80C52 80C32/80C52 Diagrams are for reference only. Package sizes are not to scale. DIL LCC Flat Pack P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/A0 P0.1/A1 P0.2/A2 P0.3/A3 P0.4/A4 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.5/A5 P0.6/A6 P0.7/A7 EA NC ALE PSEN P2.7/A14 P2.6/A13 P2.5/A12 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC P2.0/A7 P2.1/A8 P2.2/A9 P2.3/A10 P2.4/A11 15 P 16 P 17 P 30 RxD/P 31 TxD/P 32 INT0/P 33 INT1/P 34 T0/P 35 T1/P 36 WR/P 37 RD/P XTAL2 XTAL1 SS V NC 20 P 21 P 22 P 23 P 24 P RST NC 14 P 13 P 12 P 11 P 10 P NC CC V 00 A0/P /A8 /A9 /A10 /A11 /A12 04 P /A4 05 P /A5 06 P /A6 07 P /A7 EA NC ALE PSEN 27 P /A15 26 P /A14 25 P /A13 /T2EX /T2 01 A1/P 02 A2/P 03 A3/P 80C32/80C52...
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80c32(Themic) - 80C32/80C52 Rev. G (14 Jan. 97) 1 MATRA MHS...

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