6k 316k 44 44 816k 816k 1777 1777 889 889 695 28k 811

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Unformatted text preview: a A1 A2 A B Acceleration (1 LSB lag) Settling Time (179 deg. Step) Parameter Resolution Tracking Rate BW (Closed Loop) Ka A1 A2 A B Acceleration (1 LSB lag) Settling Time (179 deg. Step) Table 5. Dynamic Characteristics Low Bandwidth Card Parameter Unit High Range 16*** 14*** 12* Bits 10* Resolution 2.5 10 40 rps. min. (typ) 160 Tracking Rate 45 45 45 Hz. norm. 45 BW (Closed Loop) 2 10.13k 10.13k 10.13k 1/sec 10.13k Ka 0.25 0.25 0.25 0.25 A1 1/sec 41.03k 41.03k 41.03k 41.03k A2 1/sec 100 100 100 100 A 1/sec 50 50 50 50 B 1/sec 55.7 222.9 891.4 3.57k Acceleration (1 LSB lag) deg/sec 308 149 92 73 Settling Time (179 deg. Step) ms typ Parameter Unit Low Range 16*** 14*** 12* Bits 10* Resolution .5 2 8 rps. min. (typ) 32 Tracking Rate 15 15 15 Hz. norm. 15 BW (Closed Loop) 2 1.11k 1.11k 1.11k 1/sec 1.11k Ka .14 .14 .14 .14 A1 1/sec 8.16k 8.16k 8.16k 8.16k A2 1/sec 33.3 33.3 33.3 33.3 A 1/sec 16.7 16.7 16.7 16.7 B 1/sec 6.11 24.43 97.71 390.83 Acceleration (1 LSB lag) deg/sec 1325 549 302 226 Settling Time (179 deg. Step) ms typ NOTES: *Exceeds tracking rate to bandwidth ratio. Selecting a bandwidth that is too low relative to the maximum application tracking rate can create a spin-around condition in which the converter never settles (particularly during initial power-up). (Refer to "Tracking/BW Relationship" table in RDC-19222S data sheet.) **High Bandwidth converters may jitter at carrier frequencies <1.5kHz ***Low Bandwidth converters may jitter at carrier frequencies <225Hz Data Device Corporation 15 SB-3631X Manual APPENDIX A TRANSFER FUNCTION The dynamic performance of the converter can be determined from its Transfer Function (Refer to Figure 8 and Figure 9). The open loop transfer function is as follows: A2 Open Loop Transfer Function = S2 ( S + 1) B S (10B + 1) where A is the gain coefficient and A2 = A1A2 and B is the frequency of lead compensation A1 Error Processor, G1 Gain = ( S + 1) B S S (10B + 1 ) VCO, G2 = A2 / S RB CBW VEL C BW /10 RS -VSUM VEL -VCO 50 pf C VCO CT RESOLVER INPUT () + GAIN DEMOD 1 CS F S 11 mV/LSB 1.25 V THRESHOLD RV R1 VCO - 16 BIT UP/DOWN COUNTER H=1 DIGITAL OUTPUT () Figure 8. Transfer Function Block Diagram #1 ERROR PROCESSOR VELOCITY OUT VCO A2 S DIGITAL POSITION OUT () RESOLVER INPUT () + - CT e A1 S + 1 B...
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