Sb 3631x card assembly data device corporation 23 sb

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Unformatted text preview: cal Base Address and Offset fashion. Each read/write register is 16 Bits wide. The Register Map of the I/O registers is detailed in the following tables. Table 11. Register Map Functions Register 1 2 3 4 5 HEX Offset 00 02 04 06 08 Read/Write Function Channel Select and Inhibit (Read/Write) Bandwidth and Resolution (Read/Write) Status Register (Read Only) 8 Bit Discrete I/O (Read/Write) Angle Data (Read Only) Data Device Corporation 25 SB-3631X Manual Ch Sel MSB 0 0 1 1 1 4 0 3 1 2 0 1 Data Device Corporation Ch Sel LSB Selected Channel HEX Offset 00 INH All BW 4 Res Res Ch 4 Ch 4 B A BW 3 BW 2 O/P 6 (r) O/P 4 (r) O/P 8 (w) O/P 8 (r) D15 (r) D14 (r) D11 (r) D13 (r) D12 (r) D10 (r) O/P 7 (r) O/P 6 (r) O/P 4 (r) O/P 3 (r) O/P 5 (r) O/P 2 (r) D9 (r) O/P 1 (r) D8 (r) I/P 8 (r) D7 (r) O/P 3 (r) O/P 5 (r) O/P 2 (r) O/P 1 (r) O/P 7 (w) I/P 7 (r) D6 (r) O/P 6 (w) I/P 6 (r) D5 (r) O/P 5 (w) I/P 5 (r) D4 (r) Res Res Ch 3 Ch 3 B A INH 4 INH 3 INH 2 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INH 1 BW 1 Ch Sel MSB Ch Sel LSB Res Res Ch 1 Ch 1 B A BIT 4 (r) O/P 4 (w) I/P 4 (r) D3 (r) BIT 3 (r) O/P 3 (w) I/P 3 (r) D2 (r) BIT 2 (r) O/P 2 (w) I/P 2 (r) D1 (r) BIT 1 (r) O/P 1 (w) I/P 1 (r) D0 (r) 02 Res Res Ch 2 Ch 2 B A 04 O/P 8 (r) O/P 7 (r) Register # Function 1 Channel Select and Inhibit 2 Bandwidth and Resolution 3 Discrete Output Read-back and BIT 06 Table 12. Register Map 26 06 08 Res CH X (B) 0 0 1 1 Res CH X (A) 0 1 0 1 Resolution 10 12 14 16 4 (Write) Discrete Output Write 4 (Read) Discrete Output Read-back / Input Read 5 Read Angle APPENDIX D SB-3631X Manual APPENDIX E Synchro/Resolver Input Configuration The input configuration for each channel on the SB-3631X is determined by the thin film resistor network position on the card. Each channel has two possible positions for the thin film network to be installed on the card. When viewing the card with the J1/P1 and J2/P2 connectors facing down, the left hand socket is for the synchro input and the right hand socket is for the resolver input (refer to Figure 17). Note: Channels 1, 2, and 3 have two sockets offset by 0.1", and c...
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This note was uploaded on 08/12/2009 for the course IQ 343242 taught by Professor Zeruela during the Spring '09 term at Universidade de Brasília.

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