lec03_Mips_Architecture

lec03_Mips_Architecture - Lecture 3: Instructions and...

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Lecture 3: Instructions and Operations MIPS Architecture Chapter 3 Computer Architecture Csc 205
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Instruction Set Architecture: What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction ° Instruction Format or Encoding – how is it decoded? ° Location of operands and result – where other than memory? – how many explicit operands? – how are memory operands located? – which can or cannot be in memory? ° Data type and size ° Operations – what are supported? ° Successor instruction – what instruction is executed next?
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MIPS Architecture - Registers and Memory ° The MIPS architecture is considered to be a typical RISC architecture. Simplified instruction set => easier to study Most new machines are RISC ° Programmable storage 31 x 32-bit GPRs (r0 = 0) special purpose - HI, LO, PC 32 x 32-bit FP regs 2^32 x bytes of memory ° Memory is byte addressable Words are 32 bits = 4 bytes Words start at multiple of 4 address r0 r1 ° ° ° r31 PC lo hi f0 f1 ° ° ° f31 00…0000 00. ..0100 00…1000 11…1000 32 bits
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MIPS Addressing Modes ° Addressing modes specify where the data used by an instruction is located. mode example action register direct add $s1, $s2, $s3 $s1 = $s2 + $s3 immediate addi $s1, $s2, 200 $s1 = $s2 + 200 base+index lw $s1, 200($s2) $s1 = mem[200 + $s2] PC-relative beq $s1, $s2, 200 if ($s1 == $s2) PC = PC+4+200*4 Pseudo-direct j 4000 PC = (PC[31:28], 4000*4) ° Often, the type of addressing mode depends on the type of operation being performed (e.g., branches all use PC relative) ° A summary of MIPS addressing modes is given on the back cover of the book.
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Generic Examples of Instruction Format Widths Variable: Fixed: Hybrid: What are the advantages and disadvantages of each type of format?
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MIPS Addressing Modes/Instruction Formats op rs rt rd immed register Register (direct) op rs rt register Base+index + Memory immed op rs rt Immediate immed op rs rt PC PC-relative + Memory All MIPS instructions are 32 bits wide - fixed length add $s1, $s2, $s3 addi $s1, $s2, 200 lw $s1, 200($s2) beq $s1, $s2, 200
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MIPS Instruction Fields : R-Type and I- type ° Register type (R-type) and immediate type (I-type) instructions have the following formats: shamt funct 6 bits 5 bits rd 5 bits rt 5 bits rs 5 bits op 6 bits field meaning op Basic operation of the instruction (opcode) rs First register source operand rt Second register source operand rd Register destination operand (gets result) shamt: Shift amount funct Function field - selects the variant of the operation in the op field (function code) immed Immediate value immed rt rs op R-type I-type
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Register Names in MIPS Assembly Language ° With MIPS, there is a convention for mapping register names into general purpose register numbers. name
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This note was uploaded on 08/12/2009 for the course CS 205 taught by Professor H.shaban during the Spring '07 term at Northern Virginia.

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lec03_Mips_Architecture - Lecture 3: Instructions and...

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