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lec06_Multiplication_Divion

lec06_Multiplication_Divion - Lecture 6 Multiply Shift and...

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Lecture 6: Multiply, Shift, and Divide CSC 205
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1-bit ALU for MSB (correction) ° The ALU for the MSB must also detect overflow and indicate the sign of the result. 7 i a i b i c i r 1 + i c 0 1 2 i less 3 0 , 1 ALUop 2 ALUop V set 1 - = n n c c V ) ( B A set < =
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MIPS instructions ° Instruction Example Meaning Comments ° multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product ° multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product ° divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder ° Hi = $2 mod $3 ° divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder ° Hi = $2 mod $3 ° Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi ° Move from Lo mflo $1 $1 = Lo Used to get copy of Lo ° shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant ° shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant ° shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) ° shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable ° shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable ° shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable
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MULTIPLY (unsigned) ° Paper and pencil example (unsigned):    Multiplicand                     1000 = 8 Multiplier 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 ° n bits x n bits = 2n bit product ° Binary makes it easy: 0 => place 0 ( 0 x multiplicand) 1 => place a copy ( 1 x multiplicand) ° 4 versions of multiply hardware & algorithm: successive refinement
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Unsigned Combinational Multiplier ° Stage i accumulates A * 2 i if B i == 1 ° Q: How much hardware for 32 bit multiplier? B 0 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 B 1 B 2 B 3 P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 0 0 0 0
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How does it work? ° at each stage shift A left ( x 2) ° use next bit of B to determine whether to add in shifted multiplicand ° accumulate 2n bit partial product at each stage B 0 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 A 0 A 1 A 2 A 3 B 1 B 2 B 3 P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 0 0 0 0 0 0 0
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Unisigned shift-add multiplier (version 1) ° 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Product Multiplier Multiplicand 64-bit ALU Shift Left Shift Right Write Control 32 bits 64 bits 64 bits Multiplier = datapath + control
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Multiply Algorithm Version 1 ° Product Multiplier Multiplicand 0000 0000 0011 0000 0010 ° 0000 0010 0001 0000 0100 ° 0000 0110 0000 0000 1000 ° 0000 0110 3. Shift the Multiplier register right 1 bit. Done Yes: n repetitions 2. Shift the Multiplicand register left 1 bit. No: < n repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to product & place the result in Product register n th repetition? Start
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Observations on Multiply Version 1 ° 1 clock per cycle => 100 clocks per multiply ° 1/2 bits in multiplicand always 0 => 64-bit adder is wasted ° 0’s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed ° Instead of shifting multiplicand to left, shift product to right.
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MULTIPLY HARDWARE Version 2 ° 32 -bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Product Multiplier Multiplicand 32-bit ALU Shift Right Write Control 32 bits 32 bits 64 bits Shift Right
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