lec08_Single_Cycle_Processor

lec08_Single_Cycle_Processor - Lecture 8: Designing a...

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Lecture 8: Designing a Single Cycle Datapath Computer Architecture CSC 205
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The Big Picture: Where are We Now? ° The Five Classic Components of a Computer ° Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output inst. set design technology machine design
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The Big Picture: The Performance Perspective ° Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction ° Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction ° Single cycle processor - one clock cycle per instruction Advantages: Simple design, low CPI Disadvantages: Long cycle time, which is limited by the slowest instruction. CPI Inst. Count Cycle Time
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How to Design a Processor: step-by- step ° Analyze instruction set => datapath requirements the meaning of each instruction is given by register transfers R[rd] <– R[rs] + R[rt]; datapath must include storage element for ISA registers datapath must support each register transfer ° Select set of datapath components and establish clocking methodology ° Design datapath to meet the requirements ° Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ° Design the control logic
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Review: The MIPS Instruction Formats ° All MIPS instructions are 32 bits long. The three instruction formats are: R-type I-type J-type ° The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
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Step 1a: The MIPS Subset for Today ° ADD and SUB addu rd, rs, rt subu rd, rs, rt ° OR Immediate: ori rt, rs, imm16 ° LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 ° BRANCH: beq rs, rt, imm16 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits For the class project, we will be designing a processor that supports a larger subset of the MIPS instruction set.
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Register Transfer Logic (RTL) ° RTL gives the meaning of the instructions ° All instructions start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers addu R[rd] <– R[rs] + R[rt]; PC <– PC + 4 subu
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lec08_Single_Cycle_Processor - Lecture 8: Designing a...

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