lec09_Single_Cycle_Processor_Control

lec09_Single_Cycle_Processor_Control - Lecture 9: Single...

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Lecture 9: Single Cycle Control Computer Architecture Csc 205
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A Single Cycle Datapath ° We have everything except control signals ( underlined ) Today’s lecture will look at how to generate the control signals 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction<31:0> 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt nPC_sel
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RTL: The Add Instruction ° add rd, rs, rt mem[PC] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next instruction’s address op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
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Instruction Fetch Unit at the Beginning of Add PC Ext ° Fetch the instruction from Instruction memory: Instruction <- mem[PC] ° Done for all instructions => Don’t need special control bits Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction<31:0>
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The Single Cycle Datapath during Add/Sub 32 ALUctr = Add Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 1 Extender Mux Mux 32 16 imm16 ALUSrc = 0 ExtOp = x MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction<31:0> ° R[rd] <- R[rs] op R[rt] 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt op rs rt rd shamt funct 0 6 11 16 21 26 31 nPC_sel= +4
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Instruction Fetch Unit at the End of Add ° PC <- PC + 4 This is the same for all instructions except Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel = +4 imm16 Instruction<31:0>
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The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 0 Extender Mux Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction<31:0> ° R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt op rs rt immediate 0 16 21 26 31 nPC_sel= +4
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The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 0 Extender Mux Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction<31:0> 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt ° R[rt] <- Data Memory {R[rs] + SignExt[imm16]} op rs rt immediate 0 16 21 26 31 nPC_sel= +4
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This note was uploaded on 08/12/2009 for the course CS 205 taught by Professor H.shaban during the Spring '07 term at Northern Virginia.

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lec09_Single_Cycle_Processor_Control - Lecture 9: Single...

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