lec12_Pipeline_DataPath_Design

lec12_Pipeline_DataPath_Design - Lecture 12: Pipeline...

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Unformatted text preview: Lecture 12: Pipeline Datapath Design Computer Architecture Csc 205 Designing a Pipelined Processor Go back and examine your datapath and control diagram associated resources with states ensure that flows do not conflict, or figure out how to resolve assert control in appropriate stage Pipelined Processor (simplified for slides) What happens if we start a new instruction every cycle? Exec Reg. File Mem Access Data Mem A B S M Reg File Equal PC Next PC IR Inst. Mem Valid IRex Dcd Ctrl IRmem Ex Ctrl IRwb Mem Ctrl WB Ctrl Control and Datapath IR <- Mem[PC]; PC < PC+4; A <- R[rs]; B< R[rt] S < A + B; R[rd] < S; S < A + SX; M < Mem[S] R[rd] < M; S < A or ZX; R[rt] < S; S < A + SX; Mem[S] <- B If Cond PC < PC+SX; Exec Reg. File Mem Access Data Mem A B S Reg File Equal PC Next PC IR Inst. Mem D M Pipelining the Load Instruction The five independent functional units in the pipeline datapath are: Instruction Memory for the Ifetch stage Register Files Read ports (bus A and busB) for the Reg/Dec stage ALU for the Exec stage Data Memory for the Mem stage Register Files Write port (bus W) for the Wr stage Clock Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Reg/Dec Exec Mem Wr 1st lw Ifetch Reg/Dec Exec Mem Wr 2nd lw Ifetch Reg/Dec Exec Mem Wr 3rd lw The Four Stages of R- type Ifetch: Instruction Fetch Fetch the instruction from the Instruction Memory Update PC Reg/Dec: Registers Fetch and Instruction Decode Exec: ALU operates on the two register operands Wr: Write the ALU output back to the register file Cycle 1 Cycle 2 Cycle 3 Cycle 4 Ifetch Reg/Dec Exec Wr R-type Pipelining the R-type and Load Instruction We have pipeline conflict or structural hazard: Two instructions try to write to the register file at the same time! Only one write port Clock Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Ifetch Reg/Dec Exec Wr R-type Ifetch Reg/Dec Exec Wr R-type Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Wr R-type Ifetch Reg/Dec Exec Wr R-type Ops! We have a problem! Important Observation Each functional unit can only be used once per instruction Each functional unit must be used at the same stage for all instructions:...
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This note was uploaded on 08/12/2009 for the course CS 205 taught by Professor H.shaban during the Spring '07 term at Northern Virginia.

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lec12_Pipeline_DataPath_Design - Lecture 12: Pipeline...

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