lec14Memory_Hierachy_Cache_Design

lec14Memory_Hierachy_Cache_Design - Lecture 14 Memory...

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Lecture 14 Memory Hierarchy and Cache Design Computer Architecture Csc 205
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The Five Classic Components of a Computer Memory is usually implemented as: Dynamic Random Access Memory (DRAM) - for main memory Static Random Access Memory (SRAM) - for cache The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output
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Technology Trends (from 1st lecture) DRAM Year Size Cycle Time 1980 64 Kb 250 ns 1983 256 Kb 220 ns 1986 1 Mb 190 ns 1989 4 Mb 165 ns 1992 16 Mb 145 ns 1995 64 Mb 120 ns 1998 256 Mb 100 ns 2001 1 Gb 80 ns Capacity Speed (latency) Logic: 2x in 3 years 2x in 3 years DRAM: 4x in 3 years 2x in 10 years Disk: 4x in 3 years 2x in 10 years 1000:1! 2:1!
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µProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Time “Moore’s Law” Processor-DRAM Memory Gap (latency) Who Cares About Memory?
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Today’s Situation: Microprocessors Rely on caches to bridge gap Cache is a high-speed memory between the processor and main memory Microprocessor-DRAM performance gap time of a full cache miss in instructions executed 1st Alpha (7000): 340 ns/5.0 ns = 68 clks x 2 or 136 instructions 2nd Alpha (8400): 266 ns/3.3 ns = 80 clks x 4 or 320 instructions 3rd Alpha (t.b.d.): 180 ns/1.7 ns =108 clks x 6 or 648 instructions 1/2X latency x 3X clock rate x 3X Instr/clock -5X
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An Expanded View of the Memory System Control Datapath Memory Processor Memory Memory Memory Fastest Slowest Smallest Biggest Highest Lowest Speed: Size: Cost:
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Memory Hierarchy: How Does it Work? Temporal Locality (Locality in Time): => Keep most recently accessed data items closer to the processor Spatial Locality (Locality in Space): => Move blocks consists of contiguous words to the upper levels Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y
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Memory Hierarchy: Terminology Hit : data appears in some block in the upper level (example: Block X) Hit Rate : the fraction of memory access found in the upper level Hit Time : Time to access the upper level which consists of RAM access time + Time to determine hit/miss Miss : data needs to be retrieve from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) Miss Penalty : Time to replace a block in the upper level + Time to deliver the block the processor Hit Time << Miss Penalty Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y
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Memory Hierarchy of a Modern Computer System By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology.
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This note was uploaded on 08/12/2009 for the course CS 205 taught by Professor H.shaban during the Spring '07 term at Northern Virginia.

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lec14Memory_Hierachy_Cache_Design - Lecture 14 Memory...

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