HO21_315aSP09_layout_2 - Layout – Part II Design Related...

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Unformatted text preview: Layout – Part II: Design Related Issues Class Summary David Su & Boris Murmann Stanford University Copyright © 2009 EE315A ― HO #21 D. Su & B. Murmann 1 Overview • Noise coupling effects • Latchup • ESD • Class Summary D. Su & B. Murmann EE315A ― HO #21 2 Noise Interference Noise Coupling Noise Source Sensitive S iti Circuits D. Su & B. Murmann EE315A ― HO #21 3 Noise Coupling Mechanisms • Capacitive – E.g. through on-chip wire crosstalk • Inductive – E.g. through bond wires • Supply coupling – Modulation of supplies due to IR or Ldi/dt drop • Substrate coupling D. Su & B. Murmann EE315A ― HO #21 4 Capacitive Coupling -- Bias Vx Low cap: fast recovery big bounce t Vx High cap: slow recovery small bounce Noise Coupling • • • t Can use decoupling capacitors to reduce the amplitude of noise coupling into bias nodes If noise is "deterministic" and occurs at a “don’t care point in time you deterministic don t care” time, might be better off not decoupling, but making the bias node "fast" (small mirror ratio, no decoupling cap) so it can recover quickly Must go for either extreme case: no decoupling or large decoupling D. Su & B. Murmann EE315A ― HO #21 5 Capacitive Coupling -- SC Charge conservation node • Must minimize coupling into charge conservation node – Proper placement of “bottom plate” parasitics – Substrate shielding D. Su & B. Murmann EE315A ― HO #21 6 Capacitor Parasitics E.g. α~1%, β~10% for a MIM capacitor [Ng, Trans. Electron Dev., 7/2005] D. Su & B. Murmann EE315A ― HO #21 7 Proper Configuration Keep wiring as short as possible and do not cross with any other signal May want to place a “clean” shield between wires and substrate D. Su & B. Murmann EE315A ― HO #21 8 Layout Gregorian & Temes, pp. 518, 524 Can use metal shield in a modern process t protect coupling to to t t li t output. Such a shield is usually not needed when the signals are differential D. Su & B. Murmann EE315A ― HO #21 9 Floorplanning • • • • • A common mistake is to do a great job of laying out lots of little cells but then make a big mess when pulling the design together A good floorplan is essential to being able to quickly make a good layout with few iterations A floorplan is an evolving document that helps the designer organize the chip into pieces that fit together well – Don’t be afraid to change it as you go along and discover new issues, just start out with one so you don’t miss the obvious things that can be very painful later Know when to stop! You can easily get so carried away with these issues that your layout takes a very long time to complete The key is to do what is right for the application – An RF mixer should minimize capacitance – A 14-bit A/D converter needs well a very balanced layout – … D. Su & B. Murmann EE315A ― HO #21 10 Inductive Coupling through Bondwires Package Silicon Bond Wire Silicon Bondwire Leadframe PCB Leadframe Source: Lawrence Larson, ISSCC 2009 SET • The leadframe/wirebond interface may require careful modeling • Ground pin is not “ground” (~1 nH/mm) • Significant mutual coupling between two adjacent traces (K ~ 0.4) • Parallel ground bonds is not very effective (reduction to ~0.7L) • Sometimes better off keeping sensitive signals on chip • E.g. VCO control voltage D. Su & B. Murmann EE315A ― HO #21 11 Test/Application Board • • • • • Planning begins with chip pin-out – Uhps, my analog pin is right next to a digital output... Not "black magic", but weeks of design time and "thinking" Key aspects – Supply/ground routing – Bypass capacitors – Coupling between signals Good idea to look t G d id t l k at vendor d t h t for example d datasheets f l layouts/schematics/application notes For good practices on how to avoid issues see e.g. – Analog Devices Application Note 345: "Grounding for Low-and-High-Frequency Circuits“ – A Practical Guide to High-Speed Printed-Circuit-Board Layout, http://www.analog.com/library/analogDialogue/archives/39-09/layout.html D. Su & B. Murmann EE315A ― HO #21 12 Vendor Eval Bord Layout [Analog Devices AD9235 Data Sheet] D. Su & B. Murmann EE315A ― HO #21 13 Supply Noise • • • Typical culprits – Digital logic g g – Clocks – IO pads Preventive measures – Reduce noise by turning off unused digital logic • Clock gating, etc. – Avoid oversized digital buffers (large current spikes high spikes, frequency content) – Stagger digital switching in time; try to minimize activity at certain instants (e g when sampling switch opens) (e.g. Avoid large number of digital pads switching simultaneously – Work with “current mode” outputs where possible D. Su & B. Murmann EE315A ― HO #21 14 LVDS Outputs Helps minimize dynamic currents y due to I/O Cost: additional pin Analog Devices Application Note 586: "LVDS Data Outputs for High Speed ADCs" D. Su & B. Murmann EE315A ― HO #21 15 Basic View of Supply Noise BAD BETTER Gregorian & Temes, p. 515 D. Su & B. Murmann EE315A ― HO #21 16 Proper GND Separation M. Ingels and M.S.J. Steyaert, "Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's," IEEE J. Solid-State Circuits, pp.1136-1141, July 1997. D. Su & B. Murmann EE315A ― HO #21 17 On-Chip Decoupling Cornell et al ISSCC 2002 al, D. Su & B. Murmann EE315A ― HO #21 18 IR Drop Issues – Mirror Example I1 V1 V2=V1 I2 ΔI = I 1 − I 2 ≅ g mVwire M1 M2 - Vwire + ΔI I1 ≅ gm Vwire I1 Rwire I • Want small gm/ID ("large gate voltage overdrive") to ( large overdrive ) mitigate errors due to wire IR drop – Unfortunately this means large Vmin D. Su & B. Murmann EE315A Lecture#21 EE 214 ― HO 13 19 Current Distribution (1) • • Typically, we'll only have one single reference current generator on a chip Can generate/distribute currents across chip in two different ways – Distribute gate voltage • Can cause big p g problems due to IR drop and p p process gradients • Usually limited to local distribution – Distribute currents • Have one global bias cell close to reference that sends currents into local biasing sub-circuits • Disadvantage: consumes additional current D. Su & B. Murmann EE315A Lecture#21 EE 214 ― HO 13 20 Current Distribution (2) Iref D. Su & B. Murmann EE315A Lecture#21 EE 214 ― HO 13 21 Substrate Noise http://www-tcad.stanford.edu/tcad/pubs/theses/iorga.pdf D. Su & B. Murmann EE315A ― HO #21 22 Substrate Types "Epi Substrate" D. Su & B. Murmann EE315A ― HO #21 23 Epitaxial Substrate D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise i mixed-signal i t i in i d i l integrated circuits," IEEE J t d i it " Journal of S lid St t Circuits, vol. 28 pp. 420 - 430 A il 1993 l f Solid-State Ci it l 28, 430, April 1993. D. Su & B. Murmann EE315A ― HO #21 24 Observed Waveforms • Current disturbance roughly ± 1% D. Su & B. Murmann EE315A ― HO #21 25 Coupling vs. Distance • Essentially independent of distance! – Why? y D. Su & B. Murmann EE315A ― HO #21 26 Current Flow in Epi-Substrate (Setup as in slide 22) • M j it of current Majority f t flows in lowresistivity wafer • Coupling is very weak function of distance D. Su & B. Murmann EE315A ― HO #21 27 Guard Ring D. Su & B. Murmann EE315A ― HO #21 28 Effect of Guard Ring Large guard L d rings increase coupling! w/o w Epi substrate D. Su & B. Murmann EE315A ― HO #21 29 Backside Contact D. Su & B. Murmann EE315A ― HO #21 30 Noise vs. L4 D. Su & B. Murmann EE315A ― HO #21 31 Summary (Epi-Substrate) • • • • Closely modeled by a "single node" The most effective way to reduce coupling in Epi-substrates to is to provide a good, low inductance backside contact Unfortunately distance and guard rings don't help much in reducing coupling If you decide to use guard rings, make sure to use dedicated guard ring potentials – Otherwise guard rings may increase coupling! D. Su & B. Murmann EE315A ― HO #21 32 Current in High Resistivity Substrate Current trough p+ channel stop D. Su & B. Murmann EE315A ― HO #21 33 Coupling vs. Distance (Epi) D. Su & B. Murmann EE315A ― HO #21 34 Effect of Guard Rings Breaks p+ channel stop implant (Epi) D. Su & B. Murmann EE315A ― HO #21 35 Example http://www.commsdesign.com/showArticle.jhtml?articleID=192200561 p g j D. Su & B. Murmann EE315A ― HO #21 36 Deep N-Well http://www.commsdesign.com/showArticle.jhtml?articleID=192200561 p g j D. Su & B. Murmann EE315A ― HO #21 37 Summary (Lightly doped substrate) • • • • Distance and guard rings can help reduce coupling significantly Must connect guard rings to quiet, dedicated potentials – Otherwise they may inject noise! Isolation and coupling effects are highly layout dependent – If substrate coupling is critical, the designer should invest a good amount of time to think about potential issues and solutions CAD tools? – Still being developed/finding commercial use D. Su & B. Murmann EE315A ― HO #21 38 Selected References • • • • • • R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344 - 353, March 1996. Balsha R. Stanisic, Nishath Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot,"Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis," IEEE Journal of Solid-State Circuits, vol. 29, pp. 226 - 238, March 1994. Kuntal Joardar, "A simple approach to modeling cross-talk in integrated circuits," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1212 - 1219, October 1994. Nishath Verghese and David J. Allstot, "Computer-aided design considerations for mixed-signal coupling in RF integrated circuits," IEEE Journal of Solid-State Circuits, vol. 33, pp. 314 - 323, March 1998. A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A scalable substrate noise coupling model for design of mixed-signal ICs," IEEE Journal of Solid-State Circuits, vol. 35, pp. 895 - 904, June 2000. Tallis Blalack et al., “On-Chip RF-Isolation Techniques,” http://www.commsdesign.com/showArticle.jhtml?articleID=192200561 D. Su & B. Murmann EE315A ― HO #21 39 Latchup Minimize RS and RW using proper guard rings! http://www.analog.com/library/analogDialogue/archives/35-05/latchup/ http://www analog com/library/analogDialogue/archives/35 05/latchup/ D. Su & B. Murmann EE315A ― HO #21 40 What is ESD? • Electrostatic discharge • Example: Charge built up on human body while walking on carpet... • Charged objects near or touching IC pins can discharge through on-chip devices • Without dedicated protection circuitry, ESD events are destructive D. Su & B. Murmann EE315A ― HO #21 41 Models 2000V 150V 500V http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf http://www tcad stanford edu/tcad/pubs/theses/chun pdf D. Su & B. Murmann EE315A ― HO #21 42 Basic Protection Circuit [http://www.ce-mag.com/archive/03/ARG/dunnihoo.html] D. Su & B. Murmann EE315A ― HO #21 43 General Architecture http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf D. Su & B. Murmann EE315A ― HO #21 44 Rail Clamp Approach D. Su & B. Murmann EE315A ― HO #21 45 Testability • How to test an SoC? • Test circuits – Probe pads p – Post fabrication: cut and short? D. Su & B. Murmann EE315A ― HO #21 46 Class Summary EE252 EE312 ... EE214 EE314 EE315A Signal Conditioning Analog Media and Transducers EE315B EE264 EE371 ... A/D Digital Processing Signal Conditioning D/A Sensors, Actuators, Antennas, Storage Media, ... D. Su & B. Murmann EE315A ― HO #21 47 Course Objective • • Acquire a thorough understanding of the basic principles, challenges and limitations in signal conditioning circuit design – Focus on concepts that are unlikely to expire – Preparation for further study of state-of-the-art "fine-tuned" realizations Strategy – Acquire basic intuition by studying a selection of commonly used circuit and design techniques – Acquire depth through a design project that entails design, optimization and thorough characterization of a filter circuit in modern technology D. Su & B. Murmann EE315A ― HO #21 48 Course Topics • Continuous time filters – Biquad and ladder-based designs ladder based – Active-RC and Gm-C filters • Switched capacitor filters – A Approximation errors i i – Circuit simulation (periodic ac and noise analysis) • • Design of Operational Transconductance Ampilfiers (OTAs) – Analysis and design of fully differential implementations – Gm/ID-based optimization (BW – noise – power dissipation) Dynamic offset cancellation techniques • Sensor interface examples • Layout techniques EE315A ― HO #21 D. Su & B. Murmann 49 CT Filters • • • “Too many” architectures and circuit realizations to chose from Circuits used in practice – Sallen-Key (beware of sensitivity issues) – Known biquads (e.g. Tow-Thomas) – Ladder filters Decide on integrator realization based on specs [Kuhn, IEEE TCAS II, 10/2003] – Need good linearity Active RC – Need maximum speed Gm-C • Concepts – Sensiti it anal sis Sensitivity analysis – State-space realization – DR scaling, ordering D. Su & B. Murmann EE315A ― HO #21 50 SC Filters • • • • • Advantages – Response depends on fclk and capacitor ratios (no need to tune) – No resistive loads Disadvantages – Noise folding g – Clock ( coupling?) Analysis of nonidealities can be challenging Simulation using PAC and PNOISE – Do not start unless you have calibrated the simulator with a “hello world” example Concepts – Charge conservation – Aliasing – s z mapping (e.g. LDI) frequency warping (e g LDI), EE315A ― HO #21 D. Su & B. Murmann 51 Choosing an Implementation Discrete active RC filters Switched-capacitor filters Integrated active RC filters Integrated active Gm-C filters Passive LC filters (discrete) Passive LC filters (integrated) Distributed (waveguide) filters 1kHz D. Su & B. Murmann 1MHz 10MHz 100MHz EE315A ― HO #21 1GHz 10GHz 52 OTA Design • • • • Look-up-table-based design – gm/ID fT Systematic (iterative) design flow using a design script – Don’t be shy to make reasonable approximations based on your understanding of the circuit Stability – Usually want ~1st order behavior near loop crossover – Load compensation (single-stage) versus Miller compensation (two-stage) Noise ~ αkT/C D. Su & B. Murmann EE315A ― HO #21 53 Sensor Interfaces • • • • Borrow many concepts/requirements from filter circuits – Amplifiers noise analysis, … Amplifiers, analysis Use special tricks like chopping, CDS to enable accurate processing of “small” signals System view is key – Look at opportunities to wrap feedback around sensors • E.g. force feedback in inertial sensor, heater feedback in wind sensor, etc. Many new applications emerging – Driven by bio, energy, “smart materials”, ambient intelligence, … D. Su & B. Murmann EE315A ― HO #21 54 The Next Wave? P. Saffo, "Sensors: The next wave of infotech innovation," Institute of the Future, Menlo Park, CA. D. Su & B. Murmann EE315A ― HO #21 55 The Future? D. Su & B. Murmann EE315A ― HO #21 56 ...
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  • Spring '09
  • BorisMurmann
  • Capacitors, Electronic design automation, B. Murmann, Electromagnetic compatibility, Substrate coupling

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