HO12_315aSP09_OTA_prelims

HO12_315aSP09_OTA_prelims - OTA Design Preliminaries Boris...

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Unformatted text preview: OTA Design Preliminaries Boris Murmann Stanford University [email protected] Copyright © 2009 by Boris Murmann EE315A ― HO #12 B. Murmann 1 Outline of OTA Design Lectures • Basic considerations – Application requirements for OTAs used in filters – The case f fully differential circuits for f ff • Transistor models, gm/ID-based design • Single-stage OTAs g g – Basic differential pair – Telescopic architecture – Folded cascode architecture • Two-stage OTA • Common mode feedback implementation • Advanced techniques – Gain boosting – Ahuja compensation – Three stage architectures Three-stage B. Murmann EE315A ― HO #12 2 OTA Application in Filters Active RC Gm-OTA-C C R RL Switched Capacitor EE315A ― HO #12 B. Murmann 3 Requirements (1) Active RC Gm-OTA-C OTA C SC High gain X X X Low noise X X X High BW X X X Capacitive loads X X X Resistive loads X Fast settling B. Murmann X EE315A ― HO #12 4 Requirements (2) • Special requirements in active-RC and SC circuits p q – Tend to narrow design space • Active RC resistive loads – Difficult to achieve sufficient gain with a single-stage OTA • SC fast transient settling – Must stay away from “tricks” such as pole-zero cancellation tricks pole zero • Pole zero doublets can cause long setting tails (more later) – Hard to achieve fast settling for three or more stages • We will take these issues into account as we discuss the various OTA implementation styles B. Murmann EE315A ― HO #12 5 Fully Differential vs. Single Ended vin vout • Symmetrical – Immune to coupling and power supply noise – Easy to analyze – Can invert signal via wire crossing – Requires common mode feedback (CMFB) B. Murmann • Lower complexity (component count) • Can build non-inverting unity gain buffer without using any feedback components EE315A ― HO #12 6 Coupling Noise Single Ended Signaling Differential Signaling Vaggressor Ccouple Vaggressor Vi Ccouple Vip Vim • Vic Vid (!) Similar arguments can be made regarding the rejection of supply noise, ground bounce, substrate noise, etc. B. Murmann EE315A ― HO #12 7 Fully Differential vs. Single Ended • Most precision analog integrated circuits are based on fully p g g y differential stages – Filters, data converters, etc. • In I contrast, printed circuit board circuits t d t b single ended t t i t d i it b d i it tend to be i l d d – Want minimum complexity and component count • Since this course (and also EE315B) emphasizes integrated ( ) p g circuit design, we will tailor our analyses toward fully differential implementations B. Murmann EE315A ― HO #12 8 Transistor Sizing Gm = gm1a = gm1b • Typical problem – Want to realize a certain amount of gm – Need to determine W L ITAIL W, L, • Classical square-law equations are very inaccurate for modern technologies gm = 2IDμCox B. Murmann W L EE315A ― HO #12 9 The Problem Hundreds of parameters! B. Murmann EE315A ― HO #12 10 The Solution • Use pre-computed spice data in hand calculations EE315A ― HO #12 B. Murmann 11 MOSFET Small-Signal Model Cgg B. Murmann Cgs + Cgb + Cgd Cdd EE315A ― HO #12 Cdb + Cgd 12 Figures of Merit for Transistors Square Law • Current efficiency – Want large gm, for as little current as possible • Transit frequency – Want large gm, without large Cgg • Intrinsic gain – Want large gm, but no gds gm ID = 2 VOV gm Cgg ≅ 3 μVOV 2 L2 gm g ds ≅ 2 λVOV B. Murmann 13 Technology Characterization for Design • Plot the following parameters for a reasonable range of gm/ID and channel lengths – Transit frequency (ωT = gm/Cgg) – Intrinsic gain (gm/gds) – Current density (ID/W) y( ) • In addition, tabulate relative estimates of extrinsic capacitances – Cgd/Cgg and Cdd/Cgg • Parameters are (to first order) independent of device width – Enables "normalized design" and re-use of charts – Somewhat similar to filter design procedure using normalized coefficient tables • Do “hand calculations” using the generated technology data – C use M tl b f Can Matlab functions f t bl l k ti for table-look-up B. Murmann EE315A ― HO #12 14 Testbench (DC Sweep) Sweep M1 DD Sweep • Useful trick for Cadence/Spectre – Add an include file containing the line “save M1” to save all device parameters across the sweep (gm, Cgg, …) EE315A ― HO #12 B. Murmann 15 NMOS Transit Frequency Chart NMOS, 0.18...0.5um, step=20nm 25 f T [GHz] 20 L=0.18um 15 10 5 L=0.5um 5 10 15 20 gm/I D [S/A] B. Murmann EE315A ― HO #12 16 PMOS Transit Frequency Chart PMOS, 0.18...0.5um, step=20nm 10 f T [GHz] 8 L=0.18um 6 4 2 L=0.5um 5 10 15 20 gm/I D [S/A] EE315A ― HO #12 B. Murmann 17 NMOS Intrinsic Gain Chart NMOS, 0.18...0.5um, step=20nm 100 L=0.5um 90 gm/gds 80 70 60 50 40 30 5 L=0.18um 10 15 20 gm/I D [S/A] B. Murmann EE315A ― HO #12 18 PMOS Intrinsic Gain Chart PMOS, 0.18...0.5um, step=20nm 100 00 90 L=0.5um gm/gds 80 70 60 50 40 30 L=0.18um 5 10 15 20 gm/I D [S/A] EE315A ― HO #12 B. Murmann 19 NMOS Current Density Chart I D/W [A/m] / NMOS, 0.18...0.5um, step=20nm L=0.18um L 0 18 10 1 L=0.5um 5 10 15 20 gm/I D [S/A] B. Murmann EE315A ― HO #12 20 PMOS Current Density Chart PMOS, 0.18...0.5um, step=20nm 10 1 I D/W [A/m] / L=0.18um L=0 18um 10 L=0.5um 0 5 10 15 20 gm/I D [S/A] B. Murmann EE315A ― HO #12 21 VDS Dependence VDS dependence is relatively weak Typically OK to yp y work with plots generated for VDD/2 B. Murmann EE315A ― HO #12 22 Extrinsic Capacitance Estimates Again, usually OK g , y to work with estimates taken at VDD/2 If the device width is known, calculate Cgd directly: Cgd, NMOS = W⋅0.491 fF/μm Cgd, PMOS = W⋅0.657 fF/μm EE315A ― HO #12 B. Murmann 23 NMOS Extrinsic Capacitances Estimates NMOS, gm/I D=10S/A, VDS=0.9V 0.8 Cgd/Cgg 0.7 Cdd/Cgg 0.6 0.5 0.4 0.3 0.2 0.1 0 B. Murmann 0.2 0.25 0.3 0.35 L [μm] EE315A ― HO #12 0.4 0.45 0.5 24 PMOS Extrinsic Capacitances Estimates PMOS, gm/I D=10S/A, VDS=0.9V 0.8 Cgd/Cgg 0.7 Cdd/Cgg 0.6 0.5 0.4 0.3 0.2 0.1 0 0.2 0.25 0.3 0.35 L [μm] 0.4 0.45 0.5 EE315A ― HO #12 B. Murmann 25 Thermal Noise γ ≅ 0.85 γ ≅ 0.7 2 id = 4kT ⋅ γ ⋅ g m ⋅ Δf • Parameter γ depends on biasing conditions, but is roughly constant within a reasonable range of gm/ID • Models become inaccurate for sub-threshold operation B. Murmann 26 Generic Design Flow • Determine gm (from design objectives) • Pick L – Short channel – Long channel high fT (high speed) high intrinsic gain, good matching, … • Pick gm/ID (or fT) – Large gm/ID low power, large signal swing (low VDSsat) – Small gm/ID high fT (high speed) g ( g p ) • Determine ID (from gm and gm/ID) • Determine W (from ID/W, current density chart) • Many other possibilities exist (depending on circuit specifics, design constraints and objectives) B. Murmann EE315A ― HO #12 27 ...
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This note was uploaded on 08/13/2009 for the course EE 315 taught by Professor Borismurmann during the Spring '09 term at Stanford.

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