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Unformatted text preview: Single Stage OTAs
Part 2 Boris Murmann
Stanford University
murmann@stanford.edu
Copyright © 2009 by Boris Murmann EE315A ― HO #14 B. Murmann 1 C1
1p Loop Gain Simulation (STB) C0
1p I0 vin V0 OTA1
Gm:10m
a0:1000 A IPRB0
vout ft:1e9
gamma:1
C2
1p
1 Reference: M. Tian, V. Visvanathan, J. Hantgan, K.
Kundert, "Striving for smallsignal stability," IEEE Circuits
and Devices Magazine, pp. 3141, January 2001. B. Murmann EE315A ― HO #14 2 OTA versus OpAmp Noise (1) 2
v out = 1 kT
β CLtot 2
v out = ? EE315A ― HO #14 B. Murmann 3 OTA versus OpAmp Noise (2) 2
v n = 4kTRnoise Δf v out = − ωu
(βv out + v n )
s v out
vn ωu
s
=−
⎛ ωu ⎞
⎜1+ s ⎟
⎝
⎠ 2 2
v out B. Murmann ωu
∞
s
= ∫ 4kTRnoise ⋅
df → ∞
⎛ ωu ⎞
0
1+
⎜
s ⎟
⎝
⎠ EE315A ― HO #14 (!) 4 Settling Performance • In switched capacitor circuits the amplifier is subjected to
transient pulses
p • Output must “settle” within ½ clock cycle, so that a proper
voltage level is sampled on CL B. Murmann EE315A ― HO #14 5 Analysis • Assuming a single stage OTA, we have V (s )
C
1
1
A ( s ) = out
≅− s
⋅
Vin ( s )
Cf 1 + 1 1 + s
T0
ωc B. Murmann T0 = β ⋅ Gm Ro
ωc ≅ β ⋅ EE315A ― HO #14 Gm
CLtot β= Cf
Cf + Cs + Cin CLtot = CL + (1 − β ) ⋅ Cf 6 Step Response
Vout ( s ) = A( s ) ⋅ Vin ( s ) Vout ( t ) = L−1 { A( s ) ⋅Vin ( s )}
Vstep ⎫
⎧
Cs
T
Vout ( t ) = L−1 ⎨ A( s ) ⋅
⋅Vstep ⋅ 0 ⋅ 1 − e −t / τ
⎬=−
s ⎭
Cf
1 + T0
⎩ ( Ideal
Response ) τ= 1
ωc Due to
Due to
D t
Finite
Finite DC
Bandwidth
Loop Gain • Finite DC loop gain results in a static error ε0 • Finite bandwidth results in a dynamic error εd that decays with time
EE315A ― HO #14 B. Murmann 7 Graphical Illustration
Static
Error ε0 Dynamic
Error εd(t)
1 Vout/Vout,ideal
V 0.8 0.6 0.4 0.2 0
0 2 4 6 8 10 t/τ
B. Murmann EE315A ― HO #14 8 Design Considerations (1)
• Need large DC loop gain for small static error
– ε0 ≅ 1/T0

– E.g. need T0 > 1000 for better than 0.1% precision • Need small τ (large bandwidth) for fast settling • Can define “settling time” based on tolerable dynamic error
−εd ,tol = −e −ts / τ
ts = −τ ⋅ ln ( εd ,tol ) EE315A ― HO #14 B. Murmann 9 Design Considerations (2) εd,tol
1% 4.6 0.1% 6.9 0.01% 9.2 106 • ts/
/τ 13.8 Going from 1% dynamic precision to 106 necessitates only ~3x
increase in settling time B. Murmann EE315A ― HO #14 10 Design Considerations (3)
•
• A switched capacitor circuit operates in two clock phases
Fitting the required number of time constants within ½ period
lets us relate fs to a minimum b d id h requirement
l
l
i i
bandwidth
i
ts = − 1
11
⋅ ln ( εd ,max ) <
2π ⋅ fc
2 fs fc
1
> − ln ( εd ,max )
fs
π εd fc/fs 1% 1.5 0.1% 2.2 0.01% 2.9 106 4.4
EE315A ― HO #14 B. Murmann 11 Simulation Example • Using i l t
U i single stage OTA • Parameters
– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85, Vidstep=10mV B. Murmann EE315A ― HO #14 12 Result
τ= 1 CL + (1 − β ) Cf
= 21ns
β
Gm Vod ,final = −Vidstep β ⋅ GmR0
= 9.76mV
1 + β ⋅ GmR0 10 Voltage [mV]
[ 8
6
4 V id Vod (simulation)
(
) 2 Vod (theory)
0
0 50 100
Time [ns] 150 200 EE315A ― HO #14 B. Murmann 13 Another Run
• Changed CL from 10pF to 300fF
10 Vo
oltage [mV] V
V 5 id od (simulation) Vod (theory?) 0 5
0 5 10 15 20 25 Time [ns] • What s
What's this ? B. Murmann EE315A ― HO #14 14 Capacitive Feedforward
• In the first instant after the input step has been applied, the
output is completely determined by capacitive voltage division • Half circuit during initial transient Vodstep
Vidstep = Cs Cf
⋅
Cf CL Cf + CL
Cs + Cin +
Cf + CL EE315A ― HO #14 B. Murmann 15 Analysis
• Can analyze this effect in two (equivalent) ways
– Using capacitive divider to find new starting point of
exponential
– Using inverse Laplace transform of A(s) with high frequency
zero included • Recall that A(s) is more precisely given by s
C
1
z
A (s ) = − s
Cf 1 + 1 1 − s
T0
p z= 1− B. Murmann Gm
Cf p=− EE315A ― HO #14 βGm
CLtot 16 New Result
Vstep ⎫
⎧
Cs
T
Vod ( t ) = L−1 ⎨ A( s ) ⋅
⋅Vidstep ⋅ 0
⎬=−
s ⎭
Cf
1 + T0
⎩ ⎛ ⎡ p⎤
⎞
⋅ ⎜ 1 − ⎢1 − ⎥ e −t / τ ⎟
⎝ ⎣ z⎦
⎠
New 1− • CL + Cf
p CL + (1 − β ) Cf + βCf
1
=
=
=
z
CL + (1 − β ) Cf
CL + (1 − β ) Cf 1 − β Cf
Cf + CL For our example:
1
500fF
1 − 0.48
500fF + 300fF • = 1 .4 ⇒ Vod ( t = 0 ) ≅ 10mV (1 − 1.4 ) = −4mV Good agreement with simulation B. Murmann EE315A ― HO #14 17 New Settling Time
⎛
ts = −τ ⋅ ln ⎜ εd ,tol
⎜
⎝ ⎡
Cf ⎤ ⎞
⎢1 − β ⋅
⎥⎟
Cf + CL ⎦ ⎟
⎣
⎠ <1
• Settling time for given precision increases due to feedforward,
since th settling range i artificially enlarged
i
the ttli
is tifi i ll
l
d • E.g., in our simulation example, the time to settle within 0.1%
dynamic error increases from 6.9τ to 7.3τ
– Not all that significant, especially when β is low and CL is at
least comparable to Cf B. Murmann EE315A ― HO #14 18 Another Simulation
• Set Vidstep=1V (CL=10pF ⇒ insignificant feedforward to output)
1000 Vo
oltage [mV] 800 Vid
V
Vod (simulation) 600 Vod (theory?) 400
200
0
0 • 50 100
Time [ns] 150 200 What causes this discrepancy ?
EE315A ― HO #14 B. Murmann 19 Capacitive Divider at OTA Input
• Half circuit during initial transient: Vxdstep = Vidstep • Cs
Cs + Cin + Cf CL
Cf + CL V
≅ −1 500fF
= −480mV
500fF + 40fF + 500fF Initially 480mV across differential pair input!
y
p
p B. Murmann EE315A ― HO #14 20 Differential Pair Characteristics
2 ⋅ VOV • Differential output current saturates for Vid > • Beyond this point, current will be much less than that p
y
p
,
predicted
⎝
by linear model (slope at origin)
1
Slope = 1 VOV = VGS − Vt ≅ Iod/ITAIL 0 2
gm 1
2 1 √2
√2 0 1 2 √2 Vid/VOV
EE315A ― HO #14 B. Murmann 21 Differential Pair Input Voltage vs. Output Current
0
Vxd [mV] 100
200 "Slewing"
"Sl i " "Linear Settling" 300 − 400
500
0 2 2
gm
ID 50 100 150 100 150 Time [ns]
Diff. pair I od [μA] 0
100
200
300
0 50
Time [ns] B. Murmann EE315A ― HO #14 22 ID Slewing
• During "slewing", the amplifier drives its output with an
approximately constant current (equal to tail bias) • The slewing behavior ends when Vid has become smaller than
about 1.4·(2/gm/ID)
– This is the point when the differential pair reenters its "linear
region"
– Hence, the remaining portion of the settling is often called
"linear settling"
• Note that this is not meant to say that the output changes with a
constant rate during this time; it settles with a (1et/τ)
relationship • The total settling time of the amplifier in presence of slewing can
be calculated as shown in the following derivation B. Murmann EE315A ― HO #14 23 Slew Rate
• In order to find the time it takes to complete slewing, we can first
calculate the "ramp speed" at which the output changes
– This quantity is called "Slew Rate" (SR) SR = B. Murmann EE315A ― HO #14 dVod ITAIL
=
dt
CLtot 24 Slewing Time
• The input of the differential pair changes at a rate equal to β·SR,
where β is given by the usual capacitive feedback divider • Hence, the time it takes to complete slewing is given by
tslew ≅ • Vxstep − 2.8 / ( g m / ID )
β ⋅ SR In our example, we have
p ,
SR = ITAIL 200μA
V
≅
= 20
10 pF
CLtot
μs tslew = 480mV − 280mV
= 21ns
V
0.48 ⋅ 20
μs EE315A ― HO #14 B. Murmann 25 Subsequent Linear Settling
• Once slewing is completed, the differential output voltage is
Vod ,slew = Vod ,final − Vod ,lin = tslew ⋅ SR = 420mV • The final settling value in our example is roughly 1V
– Al
Almost half way there after slewing
t h lf
th
ft
l i • This means that the dynamic error budget for the remaining
settling portion (Vod,lin) has increased
– E.g. if we wanted to settle within 0.1% of the final value
(~1V), we only need to complete the remaining transient to
within 0.1%·1V/0.58V = 0.17%
– Not a very big win, usually a negligible change in the number
of required time constants
• 0.1% B. Murmann 6.9τ versus 0.17% 6.4τ EE315A ― HO #14 26 Complete Expression for Settling Time
ts = tslew + tlin ≅ Vxdstep − 2.8 / ( gm / ID ) Vxdstep = Vidstep β ⋅ SR
Cs
Cs + Cin + Cf CL
Cf + CL ⎛
V
− τ ln ⎜ εd ,tol od ,final
⎜
Vod ,lin
⎝ ≅ Vidstep ⎞
⎟
⎟
⎠ Cs
Cs + Cin + Cf <1
• Note that circuits with large closed loop gain tend to slew less
– Since Vid,step cannot be larger than Vod,final/Gain
– E.g. Vod,final=2V, Gain =8 ⇒ Vxdstep < Vidstep < 250mV
• The circuit won’t slew at all as long as gm/ID < 2.8/250mV
= 11.2 S/A B. Murmann EE315A ― HO #14 27 Design Considerations
• When slewing is an issue, it can be mitigated by biasing the
g
,
g
y
g
relevant transistors at lower gm/ID
– Increase ID, keep gm constant
– Slewing performance improves because of larger ID and
improves,
also because the differential pair input range increases
(2.8/[gm/ID])
– Small signal performance remains virtually unchanged or
improves if fT is a limiting factor (since fT increases)
– Issue
• Lower gm/ID means higher power consumption B. Murmann EE315A ― HO #14 28 Slewing in SC Filters Slewing is not a problem
provided that the waveform
has settled accurately in the
sampling instant Slewing is usually
detrimental EE315A ― HO #14 B. Murmann 29 Slewing in Output Stage (1)
K.L. Lee and R.G. Meyer, R.G., "Lowdistortion s itched capacitor filter design
switchedcapacitor
techniques," IEEE J. SolidState Circuits, vol.
20, no. 6, pp. 11031113, Dec. 1985. Ideal waveform Linear settling Initial slewing Error
proportional
to signal Error
proportional t
ti
l to
signal squared B. Murmann EE315A ― HO #14 30 Slewing in Output Stage (2)
K.L. Lee and R.G. Meyer, R.G., "Lowdistortion switchedcapacitor filter design techniques," IEEE J. SolidState
Circuits, vol. 20, no. 6, pp. 11031113, Dec. 1985.
,
,
, pp
, For improved linearity:
Increase slew rate or
reduce amplitude EE315A ― HO #14 B. Murmann 31 Bandwidth Requirements for Filter Core
• Initial slewing is not a problem provided that the waveform has
settled accurately in the sampling instant • Rough calculation
– Assume amplifier slews for Ts/4
– Assume remaining linear settling occurs for 10 time
constants (precision ~0.01%)
t t (
i i
0 01%)
10τ = T
10
1
= s =
2πfc
4 4fs f0 = 10...100 ⋅ fs • fc = 40
fs ≅ 6.4fs
2π fc ≅ 64...640 ⋅ f0 Compare to CT filter (handout 7)
fu ≅ 50...1000 ⋅ f0 B. Murmann EE315A ― HO #14 Roughly the same. 32 Slewing in a CT Filter (1) • If slewing occurs i a
l i
in
continuous time filter it
will introduce distortion
– Si il t th case
Similar to the
of the SC output
stage • Is this a real problem? EE315A ― HO #14 B. Murmann 33 Slewing in a CT Filter (2)
ˆ
v out ( t ) = Vout sin ( ωt ) iout ( t ) = CLtot dv out
ˆ
= ωCLtot ⋅ Vout cos ( ωt )
dt ˆ = ωC
ˆ
iout
Ltot ⋅ Vout • To avoid slewing, we need
ω< ˆ
iout
ID
ID
1
=
=
ωc =
ωc
ˆ C
ˆ C
g
g
Vout Ltot Vout Ltot V C
ˆ
ˆ
⋅β m
Vout ⋅ β m
out Ltot
CLtot
ID e.g. ω < B. Murmann 1
S
1 ⋅ 0.5 ⋅ 10
V
A ωc = 0.2 ⋅ ωc Not a significant constraint, since we
need ω << ωc anyway EE315A ― HO #14 34 Output Swing of Simple OTA • Available output swing depends on input and output common
p
g p
p
p
mode levels • May be limited by headroom for differential pair device (Vminn) or
(
active load (Vminp) B. Murmann EE315A ― HO #14 35 Maximum Available Swing
• Input and output common
mode adjusted such that all
devices operate at " d " of
d i
"edge" f
active region
– Well defined using long
channel model, very
h
l
d l
gradual transition in short
channels • Unfortunately, the choice of
Vic and Voc are often dictated
by the circuits that interface
with the amplifier
– E.g. Vic=Voc=1.5V Vodpp ,max = 2(VDD − Vmin p − Vmin n − Vmin t ) B. Murmann EE315A ― HO #14 36 Example Vic=Voc=VDD/2 • Assuming that we are limited by Vminn, and Vminn~VOV, the
g
y
available differential peaktopeak swing is ~4Vt • Since the transition to triode is smooth, which criterion should
we use find the "exact" output range of an amplifier?
exact
EE315A ― HO #14 B. Murmann 37 Gain vs. Output Swing DC Simulation
90 Vod/Vid [V
V/V] 80 30% 70
60 Vodpp max
odpp,max 50
40 • 1.5 1 0.5 0
Vod [V] 0.5 1 1.5 In EE315A, we arbitrarily define output range as the peaktopeak swing that causes no more than 30% drop in Vod/Vid B. Murmann EE315A ― HO #14 38 How Much Gain Can We Get?
• Small signal gain (around Vid=Vod=0)
a0 = g mn ⋅ ron ⋅ rop
ron + rop = a0n a0 = a0n 1
1
= a0n
r
g mp a0n
1 + on
1+
rop
g mn a0 p 1
g m / ID ) p a
(
0n
1+
( gm / ID )n a0 p a0 = a0n  a0n •
• for ( gm / ID ) p = ( gm / ID )n E.g. a0=a0=50, (gm/ID)n= (gm/ID)p ⇒ a0=25
Static gain error ~1/To ~1/a0 ~1/25 = 4%
– Not precise enough for many applications B. Murmann EE315A ― HO #14 39 Telescopic OTA • Voltage gain ~ (gmro)2, but smaller output range B. Murmann EE315A ― HO #14 40 Half Circuit with Capacitive Feedback
• • B. Murmann Cgdn sees significant Miller
amplification at low
frequencies
– Since Zc ~ 1/gm only at
S ce
/g o y
high frequencies
– See EE114 for a
detailed analysis
y
Solution: Neutralization EE315A ― HO #14 41 Neutralization Gray & Meyer, 5th ed., p.837 B. Murmann EE315A ― HO #14 42 High Frequency Loop Gain with Neutralization T (s ) = − v x iy iz vo
⋅
⋅ ⋅
vo v x iy iz β
= −β ⋅ Gm ⋅ p2 = − 1
1− s
p2 ⋅ −1
sCLtot
C gm '
Cy Cy ≅ Cgs + 2Cdb ≅ 3Cgs
⇒ ωp 2 ≅ B. Murmann EE315A ― HO #14 ωT
3 43 Example: fp2 = 5fc
• • B. Murmann EE315A ― HO #14 Phase margin ~ 80
degrees
– Nondominant pole
p2 is not an issue in
this case
Since ωp2 ~ωT/3, this
means that ωc (and
hence closedloop BW)
h
l
dl
cannot be higher than
~ωT/15 in this scenario 44 Example: fp2 = fc/5
• • B. Murmann Phase margin ~ 28
degrees
– Not acceptable in
practice
How much phase
margin should we
design for? EE315A ― HO #14 45 Frequency Domain Perspective
Closed
loop
gain Gray & Meyer 5th ed p 632
Meyer,
ed., p.632 ω
ωc • B. Murmann EE315A ― HO #14 Typically want phase
margin ≥ 60 degrees 46 Time Domain Perspective (1)
Step Response [Yang & Allstott, IEEE TCAS 3/90] EE315A ― HO #14 B. Murmann 47 Se
ettling Time, Relative to PM=90de
o
eg Time Domain Perspective (2)
ε d spec=0.01%
d,spec 1.6
16 ε d,spec=0.1% 1.4 • ε d,spec=1% 1.2
1
0.8 Typically want to
shoot for phase
margin ~7075
degrees 0.6
0.4
0.2
02
0
50 B. Murmann 60 70
80
Phase Margin [deg] EE315A ― HO #14 90 48 Phase Margin as a Function of ωp2
• At the crossover frequency, the dominant pole has shifted the
phase by about 90° • The nondominant pole's phase at ωc is given by tan1(ωc/ωp2)
⎛ ω ⎞
PM ≅ 180° − 90° − tan −1 ⎜ c ⎟
⎜ ωp 2 ⎟
⎝
⎠ ⎛ ωp 2 ⎞
PM ≅ tan −1 ⎜
⎟
⎝ ωc ⎠ ωp2/ωc
1 45° 2 63° 3 72° 4 76° 5 B. Murmann Approximate PM
pp 79° EE315A ― HO #14 49 “Load Compensation”
• Nondominant pole is fixed at roughly ωT/3 • The loop crossover frequency is given by ωc = β Gm
C Ltot • Increasing CLtot will lower ωc and increase ωp2/ωc, which
translates into larger phase margin
t
l t i t l
h
i • A feedback circuit in which adding additional load capacitance
improves stability is often called “load compensated”
– M
Meaning th t th l d compensates or reduces th i
i that the load
t
d
the impact
t
of phase shift from p2 B. Murmann EE315A ― HO #14 50 How Fast Can We Go?
• Let’s say we design for fc ~ 1/3 fp2 ~ 1/9 fT • At a reasonable bi
bl bias, th NMOS transit frequency in 0 18
the
t
it f
i 0.18um
technology is roughly 20 GHz (nominal process and
temperature) • Assume 0.01% settling and no slewing
fs max =
s,max • f
1 fT
20 GHz
⋅ ≅ T =
= 666 MHz
2.9 9 30
30 In practice, it is hard to go any faster than 200 MHz in 0.18um
technology
– Slewing
– Timing overhead (have somewhat less time than Ts/2)
– Margins for process variation wiring caps etc
variation,
caps, etc. B. Murmann EE315A ― HO #14 51 Folded Cascode OTA
• • EE315A ― HO #14 Advantage: Input
common mode can be
chosen without taking
away output signal range • B. Murmann High and lowfrequency
behavior i il to
b h i similar t
telescopic OTA
– But noise is much
worse If slewing is not an issue,
p
the current in the output
branches can be reduced
below ITAIL/2 52 Current Mirror OTA
• No Miller effect issues • Gm = M⋅gm
– But nondominant
pole due to mirror
scales as 1/M • Useful for
applications that don’t
don t
demand bandwidths
close to process limits • Example
– Yao, IEEE JSSC
11/2004 EE315A ― HO #14 B. Murmann 53 Noise Analysis of Basic Cascode Stage
• The analysis in the appendix shows
2
vo = 1 kT
β CLtot ωc = β • ⎛ g
ω ⎞
γ ⎜1 + m2 c ⎟
⎜
g m1 ωp 2 ⎟
⎝
⎠ g m1
CLtot ωp 2 = gm2
Cx To minimize noise from M2
– Maintain large phase margin (large ωp2/ωc)
– Make gm2 as small as possible
• B. Murmann Requires small gm/ID and costs headroom EE315A ― HO #14 54 Circuit Example ωc = 1.94 GHz
PM = 70.1 deg EE315A ― HO #14 B. Murmann 55 Noise Simulation PSD M1
Total M2 noise rolls in at high freq.
CT: Noise may be filtered out
SC: Noise will alias Total
Integral M1
M2 B. Murmann EE315A ― HO #14 56 Appendix (1)
KCL Analysis:
Given
Gi
g m1⋅ β ⋅ v o + g m2⋅ v x + s ⋅ Cx⋅ v x + in1 − in2
−g m2⋅ v x + s ⋅ CLtot ⋅ v o + in2 0 0 g m2⋅ in1 + Cx⋅ in2⋅ s
⎛
⎜−
2
⎜ Cx⋅ CLtot⋅ s + CLtot⋅ g m2⋅ s + β ⋅ g m1⋅ g m2
Find( v o , v x) → ⎜
⎜ CLtot⋅ in2⋅ s − CLtot⋅ in1⋅ s + β ⋅ g m1⋅ in2
⎜ C ⋅C ⋅s2 + C ⋅g ⋅s + β⋅g ⋅g
Ltot m2
m1 m2
⎝ x Ltot g m2⋅ in1 + Cx⋅ in2⋅ s − vo − 2 CLtot ⋅ Cx⋅ s + CLtot ⋅ g m2⋅ s + β ⋅ g m1⋅ g m2 1
β ⋅ g m1 ⎞
⎟
⎟
⎟
⎟
⎟
⎠
ωc⋅ p 2 ⋅ 2 s + s ⋅ p 2 + ωc⋅ p 2 ⋅ ⎛ in1 + in2⋅
⎜ ⎝ ⎞
⎟
p2 ⎠
s g m2 p2 Cx ωc β⋅ g m1
CLtot EE315A ― HO #14 B. Murmann 57 Appendix (2)
Noise from M1: N1 ⌠
⎮
⎮
⎮
⎮
⌡ ⌠
⎮
⎮
⎮
⎮
⎮
⌡ ∞ ⎞
⎟
⎝ β ⋅ g m1 ⎠ 4⋅ kT⋅ γ ⋅ g m1⋅ ⎛
⎜ 1 2 ωc⋅ p 2
⎛
2
⎜ s + s ⋅ p 2 + ωc⋅ p 2
⎝ ⋅⎜ 2 ⎞
⎟ df
⎟
⎠ 0 N1 ∞
2
⎛
ωo
⎜
⎜ 2
ωo
2
⎜ s + s ⋅ + ωo
Q
⎝ 2 ⎞
⎟ df
⎟
⎟
⎠ ω o⋅ Q
4 0 2
⎞ ⋅ ωc⋅ p 2
⎟ p
2
⎝ β ⋅ g m1 ⎠ 4⋅ kT⋅ γ ⋅ g m1⋅ ⎛
⎜ 1 1 kT
⋅
⋅γ
β CLtot Same result as without cascode Noise from M2 (cascode device): N2 ⌠
⎮
⎮
⎮
⎮
⌡ ∞ ⎛ 2 ⎞
ωc⋅ p 2⋅ s
1 ⎞ ⎜ ωc ⎟ ⎛
4⋅ kT⋅ γ ⋅ g m2⋅ ⎛
⋅
⎜ β⋅g ⎟ ⎜ ω ⋅p ⎟⋅⎜ 2
m1 ⎠ ⎝ c 2 ⎠ ⎜
⎝
⎝ s + s ⋅ p 2 + ωc⋅ p 2
2 0 N2 B. Murmann N1 ⋅ 2 ⎞
⎟ df
⎟
⎠ ⌠
⎮
⎮
⎮
⎮
⌡ ∞ ω o⋅ s
⎛
⎜
ω
⎜ s 2 + s ⋅ o + ω o2
Q
⎝ 2 ⎞
⎟ df
⎟
⎠ ω o⋅ Q
4 0 ωc g m2
⋅
p 2 g m1
1 EE315A ― HO #14 58 ...
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