HO15_315aSP09_two_stage_OTA

HO15_315aSP09_two_stage_OTA - Two-Stage OTAs Boris Murmann...

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Unformatted text preview: Two-Stage OTAs Boris Murmann Stanford University murmann@stanford.edu Copyright © 2009 by Boris Murmann B. Murmann EE315A ― HO #15 1 Outline • Analysis of a basic two-stage OTA y g – Loop gain with capacitive feedback – Slewing – Noise • Design example B. Murmann EE315A ― HO #15 2 (Basic) Two-Stage OTA • High gain ~ (gmro)2 • Large output range • With cascodes in stage 1 the gain becomes ~(gmro)3 EE315A ― HO #15 B. Murmann 3 AC Model with Capacitive Feedback R1 = 2ro1 ro 3 R2 = ro 2 ro 4 β= Cx = Cgs1 + 2Cgd 1 Cf Cf + Cs + Cx CLtot = CL + (1 − β ) Cf + Cdb 2 + Cdb 4 + Cgd 4 (assuming neutralization) (ignoring Cgd2 f the time being) (i i for th ti b i ) C1 = Cgs 2 + Cgb 2 + Cdb1 + Cgd 1 + Cdb3 + Cgd 3 B. Murmann EE315A ― HO #15 4 Loop Gain p1 = − Gm1R1 ⋅ g m 2R2 T (s ) = β = β ⋅ a1 ( s ) a2 ( s ) = β ⋅ a ( s ) ⎛ s ⎞ ⎛ s ⎞ ⎜1− ⎟ ⋅ ⎜1− ⎟ p1 ⎠ ⎝ p2 ⎠ ⎝ 1 R1C1 p2 = − 1 R2C2 EE315A ― HO #15 B. Murmann 5 Bode Plot of Loop Gain Mag ( jω) β ⋅ a (s ) a2 ( s ) a1 ( s ) ωp1 ωp 2 Phase ( jω) 0° ω β ⋅ a (s ) • If ωp1 and ωp2 are close t each l to h other, the loop will have a very small phase margin −90° −180° B. Murmann ω EE315A ― HO #15 6 Introducing a Dominant Pole Mag ( jω) β ⋅ a (s ) • • a2 ( s ) a1 ( s ) Phase ⎡T ( j ω) ⎤ ⎣ ⎦ ωp1 The loop then behaves close to first order system around crossover frequency – Phase margin follows from ratio ωp2/ωc ω ωp 2 ωc The problem is solved if p we somehow manage to make ωp1<< ωp2 – Or ωp2<< ωp1 0° −90° ω −180° EE315A ― HO #15 B. Murmann 7 Creating a Dominant Pole • Numerical example: β = 0 .5 fp 2 = g m1 = g m 2 = 1mS 1 = 1.6MHz 2πR2CLtot fc = C1 = • CLtot = 1pF R1 = R2 = 100k Ω fp 2 3 = 530kHz 1 2π ⋅ fp1 ⋅ R1 fp1 = PM = 72° fc = 106Hz β ⋅ Gm1R1 ⋅ Gm 2R2 = 15nF Two issues – Very low fc, which means low closed-loop bandwidth – H ge capacitor Huge • Get roughly 1fF/μm2 in CMOS technology • C1 would occupy about 4mm x 4mm ! B. Murmann EE315A ― HO #15 8 Miller Compensation R1 vx Cc C1 gm1 R2 vo gm2 CL • Purposely connect an additional capacitor between gate and drain f d i of M2 (Cc = "C "Compensation capacitor") ti it ") • Two interesting things happen – Low frequency input capacitance of second stage becomes q y p p g large – exactly what we need for low ωp1 – At high frequencies, Cc turns M2 into a “diode connected device” – low impedance, i.e. large ωp2 ! p , g B. Murmann EE315A ― HO #15 9 “Pole Splitting” Gray & Meyer, 5th edition, page 642 c B. Murmann EE315A ― HO #15 10 Intuitive Perspective Cc i=gm1vx g i=g i m1vx a(s) if vo R1 C1 - CLtot R1 gm2 if vo f(s) f ( s ) = sCf Mag jω M (j ) • a( s ) 1 f(s ) ω Feedback due to Cc forces transfer function onto 1/f(s) in regions where |a(s)f(s)| >> 1 – This reduces ωp1 and increases ωp2 EE315A ― HO #15 B. Murmann 11 Detailed Analytical Result R1 vx a (s ) = • vo = v x 1 + s ⎡(CLtot ⎣ gm1 Cc C1 R2 vo gm2 CL ⎛ C ⎞ Gm1R1 ⋅ g m 2R2 ⋅ ⎜ 1 − s c ⎟ gm2 ⎠ ⎝ + Cc ) R2 + (C1 + Cc ) R1 + g m 2R2R1Cc ⎤ + s 2R1R2 (C1CLtot + CcCLtot + CcC1 ) ⎦ Very messy; need to simplify B. Murmann EE315A ― HO #15 12 Dominant Pole Approximation • We can write the denominator as ⎛ ⎛ 1 s ⎞ ⎛ s ⎞ 1 ⎞ s2 D (s ) = ⎜1− ⎟ ⋅ ⎜1− ⎟ = 1− s ⎜ + ⎟+ p1 ⎠ ⎝ p2 ⎠ ⎝ ⎝ p1 p2 ⎠ p1p2 • Since in a practical design outcome we'll h Si i ti l d i t 'll have | 1| | 2| we can |p |<<|p |, approximate ⎛ 1 ⎞ s2 D (s ) ≅ 1− s ⎜ ⎟ + ⎝ p1 ⎠ p1p2 • With this simplification, we can now easily identify p1 and p2 by comparing the coefficients with the expression from the previous slide EE315A ― HO #15 B. Murmann 13 Result ⎛ s⎞ ⎜1− ⎟ ⎝ z⎠ a ( s ) ≅ a0 ⋅ ⎛ s ⎞ ⎛ s ⎞ ⎜1− ⎟ ⋅ ⎜1− ⎟ p1 ⎠ ⎝ p2 ⎠ ⎝ p1 ≅ − p2 − B. Murmann 1 z=+ gm2 Cc R1 (C1 + Cc ) + R2 (CLtot + Cc ) + g m 2R2R1Cc gm2 C1CLtot + C1 + CLtot Cc Right half l Ri ht h lf plane (RHP) zero ≅− ⎛ C C 1 ≅ ⎜ 1 + Ltot ωp 2 ⎝ g m 2 g m 2 EE315A ― HO #15 1 g m 2R2R1Cc CLtot C1 ⎛ ⎜ C +C ⎞ 1 Ltot ⎟ ⎜1+ Cc ⎜ ⎠ ⎜ ⎝ ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ 14 RHP vs. LHP Zero ωz 1− j ω ωz − ωz → −90 1+ j Phase Ph 0° ω ωz → +90 Phase Ph ωz ω +90° −45° +45° −90° 0° EE315A ― HO #15 B. Murmann ω ωz 15 Potential Issue with RHP Zero (1) • ωz RHP zero can significantly reduce the phase margin if it occurs before the crossover frequency Gray & Meyer, 5th edition, page 643 B. Murmann EE315A ― HO #15 16 Potential Issue with RHP Zero (2) • What does it take to push RHP zero beyond ωc? • Compare ωc t ωz C to ωc ≅ ωp1T0 ≅ βGm1R1g m 2R2 β Gm1 = g m 2R2R1Cc Cc ωz = gm2 Cc ωz 1 g m 2 = ωc β Gm1 • Pushing RHP zero beyond crossover requires gm2 > βGm1 – Not always possible or desired B. Murmann EE315A ― HO #15 17 Mitigating the Impact of RHP Zero • Somehow create unilateral feedback through Cc g – Source follower from output to drive Cc • Additional power & swing issues – Cascode compensation • Ahuja, IEEE JSSC, 12/1983 • Ribner, IEEE JSSC, 12/1984 • Turns design into complicated three pole problem three-pole • Most popular method: Use a “nulling resistor" – Pushes zero to infinity B. Murmann EE315A ― HO #15 18 Nulling Resistor (1) R1 Cc Rz vx • gm1 C1 R2 vo gm2 CL New transfer function becomes ⎛ 1 ⎞ − Rz ⎟ 1 − sCc ⎜ ⎝ gm2 ⎠ a ( s ) ≅ a0 ⋅ ⎛ ⎞ ⎛ ⎞ ⎛ s s s ⎞ ⎟ ⎜1 − ⎟ ⋅ ⎜1 − ⎟ ⋅ ⎜1− p1 ⎠ ⎝ p2 ⎠ ⎝ p3 ⎠ ⎝ • p1 and p2 unchanged, new pole p3, and a knob to tune the zero B. Murmann EE315A ― HO #15 19 Nulling Resistor (2) Gray & Meyer 5th edition page 647 Meyer, t edition, • Rz=1/gm2 pushes the zero to +∞ g p • Can use a transistor in triode region to implement resistor – Helps track process variations B. Murmann EE315A ― HO #15 20 Nulling Resistor (3) • Rz=(1+C2/Cc)/gm places zero on top of ωp2! – Cancels p2 – Good in theory, may be troublesome in practice – If the pole and zero don't fall exactly on top of each other, we g get a p pole-zero doublet • Can lead to poor transient response (more later) • Does th thi d pole matter? D the third l tt ? ωp 3 ≅ g 1 ≅ m2 RzC1 C1 ωp 3 ωc = 1 g m 2 Cc β Gm1 C1 typically >> 1 EE315A ― HO #15 B. Murmann 21 Summary – Two-Stage OTA Compensation • Using Miller compensation and nulling resistor turns the design of a two-stage OTA into a “well-behaved” design problem two stage well behaved – Loop crossover set by Cc – Non-dominant pole location depends on CLtot ωc ≅ • βGm1 Cc ωp 2 ≅ gm2 C1CLtot + C1 + CLtot Cc Important to note that increasing CL moves ωp2 to lower frequencies and hence reduces the phase margin – Big difference compared to single stage OTAs, which become “more stable” when the load capacitance is increased B. Murmann EE315A ― HO #15 22 Resistive Load • Can show that adding a resistive load at the output of stage 2 g p g helps in splitting the two poles – For small R2, smaller CC needed to obtain good phase margin g • Cost – Lower loop gain, precision EE315A ― HO #15 B. Murmann 23 Response to a Large Step Vidstep Cf Cs Vxd Vsd - Vod Cgg1 gg Vidstep Vxdstep = CLtot Vidstep ⋅ Cs CC Cs + Cgg1 + f Ltot Cf + CLtot Diff. Pair TF I od/I TAIL 1 • 0.5 0 ± 2VOV -0.5 Amplifier “slews” initially if Vxdstep > 2VOV ≅ 2 2 gm / ID -1 -1 1 0 1 V /V Vxd/VOV id OV B. Murmann EE315A ― HO #15 24 Slewing in a Two-Stage OTA (1) Slew Rate SR- = ITAIL/2CC ~ “ac” ground EE315A ― HO #15 B. Murmann 25 Slewing in a Two-Stage OTA (2) • Want Vom to slew up at the same rate that Vop slews down – Otherwise amplifier sees a large common mode and bias point disturbance • This requires IB 2 I /2 ≥ TAIL C2 + Cc Cc IB 2 ≥ B. Murmann EE315A ― HO #15 ITAIL ⎛ C2 ⎞ ⎜1+ ⎟ 2 ⎝ Cc ⎠ 26 Slewing Time SR = tslew l ITAIL Cc ⎧ ⎪0 ⎪ ⎪ =⎨ 2 2 ⎪ Vidstep − g m / ID ⎪ ⎪ β ⋅ SR ⎩ for Vidstep < 2 2 g m / ID else EE315A ― HO #15 B. Murmann 27 Total Integrated Noise • M3 • Want to minimize gm3/gm1 and gm4/gm2 for low noise – Sometimes not possible due to swing constraints (small gm4 means small (gm/ID)4, large VDSsat4) M4 Cc Rz=1/gm2 vo vi=-βvo β M1 2 vo ≅ Noise from 2nd stage may be significant for small CLtot γ p g m3 ⎞ kT 1 kT ⎛ ⋅ γn ⎜1+ ⎟+ β Cc γ n g m1 ⎠ C2 ⎝ M2 CLtot ⎡ γ p gm 4 ⎞ ⎤ ⎛ ⎢1 + γ n ⎜ 1 + ⎟⎥ γ n gm2 ⎠ ⎥ ⎢ ⎝ ⎣ ⎦ A. Dastgheib and B. Murmann, "Calculation of total integrated noise in analog circuits," IEEE Trans. on Circuits and Systems I, Vol. 55, pp. 2988-2993, Nov. 2008 B. Murmann EE315A ― HO #15 28 Dynamic Range DR = Psignal ,max Pnoise = 2 0.5 ⋅Vod ,peak 2 v od Vo peak ≤ o,peak 1 (VDD − VDSsatP − VDSsatN ) 2 Vod ,peak ≤ (VDD − VDSsatP − VDSsatN ) ⎛ 2 2 ≤ ⎜VDD − − ⎜ ( gm / ID )P ( gm / ID )N ⎝ • For VDD=1.8V, Vod,peak ~ 1V is practical – Leaves 400mV headroom across loads, restricts gm/ID > 5 B. Murmann EE315A ― HO #15 29 Design Example Cf CL Cs + Vsd - Vod + Vid Cs CL Cf Specifications: Dynamic range = 75 dB Settling time = 10 ns Dynamic Settling Error ≤ 0.1% Static Settling Error ≤ 0.5% CL≥ 1pF, Cs = Cf ≥ 1pF B. Murmann EE315A ― HO #15 30 ⎞ ⎟ ⎟ ⎠ Divide and Conquer Design Flow • Optimization in Matlab – Step 1: Small-signal design • Ignore slewing; take into account only small-signal behavior – Step 2: Large-signal design • Compute slewing time; re-optimize design g g • Simulation and implementation – Simplify simulation circuit as much as possible (while preserving all important signal path features) • • • • B. Murmann Initially use ideal common mode feedback Do not worry about exact finger partitioning of transistors Do not worry about exact structure of bias network … EE315A ― HO #15 31 Prototype Amplifier • 11 Variables: ID1, W1, L1, WL1, LL1, ID2, W2, L2, WL2, LL2, Cc B. Murmann EE315A ― HO #15 32 Summary of Design Equations (Small-Signal) DR = ts ≅ 2 0.5 ⋅ Vod ,peak 2 v od −0.7 ln( εd ,spec ) ωc (No slewing, PM≅75°) εs ≅ 1 T0 B. Murmann 2 vo ≅ γ p g m3 ⎞ kT ⎡ γ p gm 4 ⎞⎤ ⎛ 1 kT ⎛ ⋅ γn ⎜1+ ⎢1 + γ n ⎜ 1 + ⎟+ ⎟⎥ β Cc γ n g m1 ⎠ C2 ⎢ γ n gm2 ⎠⎥ ⎝ ⎝ ⎣ ⎦ ωc ≅ β g m1 Cc −1 ⎛ ωp 2 ⎞ PM ≅ tan ⎜ ⎟ ⎝ ωc ⎠ T0 = β ⋅ β= Cf Cs + Cf + Cgg1 ωp 2 ≅ gm2 C1C2 + C1 + C2 Cc g m1 gm2 ⋅ gds1 + gds 3 gds 2 + gds 4 EE315A ― HO #15 33 Optimization Approach (1) • Impossible to find a closed form solution to this design problem – Solution must be found iteratively • Iterations can be easily done using a spreadsheet or Matlab – Using table-look-up of device parameters (gm/ID, fT, …) • Partition P titi space into “primary” and “ i t “ i ” d “secondary” variables d ” i bl – Primary variables are the main knobs in your design; these have the largest impact on the critical tradeoffs – Secondary variables can be set using reasonable design choices and heuristics; subject to optimization in an “outer loop” • In the presented flow we use Cgg1 and Cgg2 as the primary optimization variables – Many other possibilities exist B. Murmann EE315A ― HO #15 34 Look-Up Functions % L fT >> lookup_gmid(tech, 'n', 0.3e-6, 10e9) ans = 8.6523 % L gm/ID >> lookup_ft(tech, 'n', 0.3e-6, 10) ans = 8.9315e+009 % L gm/ID >> lookup_idw(tech, 'n', 0.3e-6, 10) ans = 16.2440 B. Murmann EE315A ― HO #15 35 Optimization Approach (2) 1. Set values for secondary variables – L1, L2 (based on gain requirement) – gm3/gm1, gm4/gm2 – … 2. 2 Main iteration loop 1. Pick Cgg1, Cgg2 2. Compute estimates of extrinsic capacitances 3. 3 Calculate Cc based on noise spec 4. Find gm, fT based on bandwidth and phase margin 5. Table look-up of gm/ID for required fT 6. 6 Compute total current (based on gm, gm/ID) 7. Iterate, using different choices in step 1. B. Murmann EE315A ― HO #15 36 Initial Guess for Cgg1 ωc ≅ β • g m1 Cc β= Cf Cf + Cs + Cgg1 Small Cgg1 helps increase ωc – But, diminishing return if Cgg1 becomes small compared to Cs+Cf • Because small Cgg1 means smaller device less gm1 device, • A reasonable initial guess: Cgg1 = Cf+Cs – Optimum choice for a single-stage OTA • See HW5, or [Boser & Howe, IEEE JSSC 3/96] EE315A ― HO #15 B. Murmann 37 Initial Guess for Cgg2 ωp 2 ≅ gm2 C2Cgg 2 Cc + Cgg 2 + CLtot ⎛ Cgg 2 1 ≅⎜ ωp 2 ⎝ g m 2 C2Cgg 2 ⎛ ⎜ Cgg 2 + C2 C ⎞ + 2 ⎟ ⎜1 + gm2 ⎠ ⎜ Cc ⎜ ⎜ ⎝ ⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ “parallel combination” • A reasonable initial guess: Cgg2 = C2 g • For a given ωp2 target and fixed C2 – Choosing Cgg2 much smaller than C2 means excess ωT2=gm2/Cgg2 and therefore small gm/ID – Choosing Cgg2 much larger than C2 will cost excess gm2 (power) to meet ωp2 target B. Murmann EE315A ― HO #15 38 Matlab Design Script (1) % design_script.m %technology data load techchar.mat techchar mat % dc loop gain requirement a0 = 1/spec.es/beta_guess; % split gain equally gm_gds = 2*sqrt(a0) % specifications spec.dr = 75; spec.ts spec ts = 10e 9; 10e-9; ... % pick L to achieve the computed value of gm_gds for all devices (using intrinsic gain charts) choices.L1 = 0.4e-6; choices.L2 choices L2 = 0 3e 6; 0.3e-6; choices.L3 = choices.L2; choices.L4 = choices.L1; ... % design choices % noise choices.gm3_gm1 = 0.5; choices.gm4_gm2 = 0.5; ... B. Murmann EE315A ― HO #15 39 Matlab Design Script (2) % primary optimization variables cgg1_cs_plus_cf = 1; cgg2_c2 cgg2 c2 = 1; % compute required current for given design choices % (see appendix for complete code) [idtotal, m1, m2, ml1, ml2, [idtotal m1 m2 ml1 ml2 other] = two_stage_miller(cgg1_cs_plus_cf, cgg2_c2, choices, tech); >> idt t l idtotal idtotal = 0.0010447 B. Murmann EE315A ― HO #15 40 Matlab Design Script (3) m1 = m2 = cgg: cdd: gm: ft: gmid: id: idw: W: cgd: • 2.0000e-012 8 4569e 013 8.4569e-013 0.0059 4.7039e+008 18.8069 3 1431e 004 3.1431e-004 0.5368 5.8551e-004 3.7701e-013 cgg: cdd: gm: ft: gmid: id: idw: W: cgd: 1.7500e-012 8 6409e 013 8.6409e-013 0.0161 1.4597e+009 21.9751 7 3040e 004 7.3040e-004 1.0039 7.2755e-004 3.4988e-013 Large devices, biased close to weak inversion, lots of self loading – Interesting to try smaller values of Cgg1/(Cs+Cf) and Cgg2/C2 1 2 EE315A ― HO #15 B. Murmann 41 Contour Plot x 10 -4 • 10 I Dtotal 8 Near-optimum N i design point – Cgg1/(Cs+Cf)=0.3 – Cgg2/C2 =0.3 – IDtotal = 534uA 6 4 1 1 0.5 Cgg2/C2 B. Murmann 0.5 0 0 Cgg1/(Cs+Cf) EE315A ― HO #15 42 Parameter File for Spice Simulation *** ota parameters **** *** 21-Aug-2008 19:51:16 .param .param .param .param param .param .param .param .param param .param .param .param .param param .param .param .param .param param CS = 1.000000e-012 CF = 1.000000e-012 CL = 1.000000e-012 CC = 2 689790e-012 2.689790e-012 CN = 1.061561e-013 RZ = 1.643900e+002 W1 = 1.648643e-004 L1 = 4 000000e-007 4.000000e-007 ID1 = 2.430537e-004 W2 = 1.890538e-004 L2 = 3.000000e-007 ID2 = 2 909095e-004 2.909095e 004 W3 = 8.528657e-006 L3 = 3.000000e-007 W4 = 9.233185e-005 L4 = 4 000000e-007 4.000000e 007 EE315A ― HO #15 B. Murmann 43 Ma agnitude [dB B] Simulation Results (1) 80 60 40 20 0 -20 20 -40 -2 10 • 10 0 10 2 10 4 Phase [degrees] e f [MHz] 0 -50 -100 -150 10 -2 10 0 10 2 10 4 Target – fc = 77 MHz – PM = 75° – T0 > 200 • f c=67.81MHz, PM=77.77deg, T0=736 Discrepancies in fc and PM due to inaccuracy in capacitance estimates, VDS dependencies etc. – Easy to track down (and potentially fix) f [MHz] B. Murmann EE315A ― HO #15 44 P PSD [V2/Hz z] Simulation Results (2) • 10 • Discrepancy sc epa cy mostly due to flicker noise (neglected in calculation) -20 10 Sqrt(Int tegral) [μVrm ms] Target T t – DR = 75 dB 5 10 10 f [Hz] Integral=139.55uVrms, DR=74.09dB (for Vodmax=1.00V) 100 0 10 5 10 10 f [Hz] EE315A ― HO #15 B. Murmann 45 Simulation Results (3) • Vod [mV] • Target – ts = 10ns Discrepancy mostly due to error in fc, PM 5 0 0 E Error [%] Response to p small transient step (10mV) • 10 5 10 15 20 Time [ns] es=-0.14%, ts=12.33ns 25 0 -0.2 -0.4 B. Murmann 8 10 12 Time [ns] 14 EE315A ― HO #15 16 46 Remaining Tasks • Try different architectures – E.g. NMOS input stage, PMOS in output stage – Very easy to run Matlab iterations for different architectures • Run large signal simulations – Check for asymmetric slewing (and fix if needed) – Re-optimize to meet settling time specs with worst case slewing (largest signal) • Refine biasing network (finger all devices) • Implement CMFB, check for stability • Run process corners • … B. Murmann EE315A ― HO #15 47 Appendix Matlab Function “two_stage_miller” B. Murmann EE315A ― HO #15 48 Matlab Code (1) function [itotal, m1, m2, m3 , m4, other] = two_stage_miller(cgg1_cs_plus_cf, cgg2_c2, choices, tech) % Boris Murmann, 2008 , % pmos input stage (M1), nmos second stage (M2) % nmos load in first stage (M3), pmos load in second stage (M4) %feedback factor and gate capacitances beta = choices cf/(choices cf+choices cs)/(1+cgg1 cs plus cf); choices.cf/(choices.cf+choices.cs)/(1+cgg1_cs_plus_cf); m1.cgg = cgg1_cs_plus_cf * (choices.cs+choices.cf); m2.cgg = cgg2_c2 * (choices.cl+(1-beta)*choices.cf); % estimates of junction caps m1.cdd = interp1(tech.Lvector, tech.pcdd_cgg, choices.L1)*m1.cgg; m2.cdd = interp1(tech.Lvector, tech.ncdd_cgg, choices.L2)*m2.cgg; % rough estimates of load junctions using approximate width ratio % gm = ~sqrt(muCoxW/L) sqrt(muCoxW/L) % W2/W1 = (gm2/gm1)^2 * mu1/mu2 * L2/L1 m3.cdd = m1.cdd *choices.gm3_gm1^2 /tech.mun_mup * choices.L3/choices.L1; m4.cdd = m2.cdd *choices.gm4_gm2^2 *tech.mun_mup * choices.L4/choices.L2; B. Murmann EE315A ― HO #15 49 Matlab Code (2) % total capacitance at stage outputs c1 = m1.cdd + m3.cdd + m2.cgg; c2 = choices.cl + m2.cdd + m4.cdd + (1-beta)*choices.cf; % calculate cc based on noise requirement kT = 1.3806503e-23*300; ntot2 = 2*kT./c2*(tech.gamma*(1+choices.gm4_gm2)+1); % stage 1 noise and compensation cap ntot1 = choices.vodntot - ntot2; if ntot1 < 0 disp('ERROR: load cap is too small to meet noise specs'); return; end cc = 2./beta*kT*tech.gamma*(1+choices.gm3_gm1)/ntot1; %calculate gm, fT, lookup gm/ID and calculate currents m1.gm m1 gm = 1/beta*2*pi*choices fc*cc; 1/beta 2 pi choices.fc cc; k = tan(pi*choices.pm/180); m2.gm = k*2*pi*choices.fc*(c2*c1/cc +c1+c2); m1.ft = 1/2/pi*m1.gm/m1.cgg; m2.ft = 1/2/pi*m2.gm/m2.cgg; B. Murmann EE315A ― HO #15 50 Matlab Code (3) m1.gmid = lookup_gmid(tech, 'p', choices.L1, m1.ft); m2.gmid = lookup_gmid(tech, 'n', choices.L2, m2.ft); m1.id = m1.gm/m1.gmid; g g m2.id = m2.gm/m2.gmid; itotal = m1.id+m2.id; % calculate device widths m1.idw m1 idw = lookup idw(tech 'p', choices.L1, m1.gmid); lookup_idw(tech, 'p' choices L1 m1 gmid); m2.idw = lookup_idw(tech, 'n', choices.L2, m2.gmid); m1.W = m1.id/m1.idw; m2.W = m2.id/m2.idw; m1.cgd = tech.pcgd_w*m1.W; m2.cgd = tech.ncgd_w*m2.W; % load devices m3.id = m1.id; m4.id = m2.id; m3.gmid m3 gmid = m1 gmid *choices gm3 gm1; m1.gmid choices.gm3_gm1; m4.gmid = m2.gmid *choices.gm4_gm2; m3.idw = lookup_idw(tech, 'n', choices.L3, m3.gmid); m4.idw = lookup_idw(tech, 'p', choices.L4, m4.gmid); m3.W = m3.id/m3.idw; m4.W = m4.id/m4.idw; i / i B. Murmann EE315A ― HO #15 51 ...
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