HO20_315aSP09_layout_1

HO20_315aSP09_layout_1 - Layout – Part I Physical Layout...

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Unformatted text preview: Layout – Part I Physical Layout Basics David Su & Boris Murmann Stanford University Copyright © 2009 EE315A ― HO #20 D.Su & B. Murmann 1 Overview • Basics • Floorplanning – blocks, power/ground ,p g – metal density rule • Passives: resistors capacitors resistors, capacitors, • Transistors D.Su & B. Murmann EE315A ― HO #20 2 Basics Tapeout Schematics Layout y Mask as Silicon • DRC: Design Rule Check • LVS: Layout Vs Schematics • LPE: Layout Parasitic Extraction D.Su & B. Murmann EE315A ― HO #20 3 Tapeout • L Layout d t b t database i is stored in gds format • Transfer to foundry was done on magnetic tape (Tapeout) • Tape is not used today. today Photo from wikimedia.org D.Su & B. Murmann EE315A ― HO #20 4 Chip micrograph D.Su & B. Murmann EE315A ― HO #20 5 Design Rules • Design rules defines geometry in x-y dimension – Width spacing, overlap Width, i l • z dimension is pre-determined by the foundry/process • Understand design rules – Design rules: must g – Recommended rules: want – Guidelines: nice to have • F ll i d i rules ensures f Following design l functionality and ti lit d yield D.Su & B. Murmann EE315A ― HO #20 6 Floorplanning • Do planning before layout of cells – Estimate area and package pins – Organize block placement – Package choice: • • • • Size of package vs die Length of bond wire and package trace (esp. for power/gnd) Coupling between adjacent bond wire and package pins Avoid a large output signal coupling back to weak input signal g • Iterative process EE315A ― HO #20 D.Su & B. Murmann 7 Block Level Layout • For each block: – Determine pin location of each block including p p g power/gnd g • Where are the signals coming and going – Place the transistors – Plan power routing ( p g (current p ) path) • A “ground” or “vdd” label on a metal line does not change parasitic resistance or inductance • “vdd” needs decoupling capacitors to “ground” – Routing of sensitive nodes • Separate noisy (digital, clock, …) and quiet (input, bias, …) signals • Shield signal signals using ground, vdd, digital control signals that are not toggling • Decouple (add capacitors) sensitive dc signals (bias, supply) • Iterative process D.Su & B. Murmann EE315A ― HO #20 8 Reminders • Resistance (including metal / poly) V=IR ( g , ) • Inductance (long metal traces, bond wire) V = L di/dt • Capacitance (charging current) I = C dv/dt EE315A ― HO #20 D.Su & B. Murmann 9 Metal Routing • Width of metal: – Electro-migration: ~1mA/um – IR drop: ~50-100mohms/square/layer – Wide metal rule < ~10um (process dependent) but 10um use multiple layers or parallel lines • Establish metal routing ground rules to ease layout – Example: M1, M3 horizontal; M2, M4 vertical D.Su & B. Murmann EE315A ― HO #20 10 Routing Signals • Use low impedance node –E Example: route current instead of high i l t t i t d f hi h impedance d voltage nodes • Watch for IR drop in current p – Voltage headroom • Shield sensitive signals – Use return path shields – Choose vdd or gnd • Shielding adds capacitance – Consider spacing to reduce coupling D.Su & B. Murmann EE315A ― HO #20 11 CMP Effect • Chemical-Mechanical Polishing (CMP) process planarizes wafer surface after each metal layer; Otherwise, unevenness of one layer that may Oh i f l h affect the next layer • Relative hardness of metal and oxide affects the polishing • Solution: – M t l coverage rule: K Metal l Keep relatively uniform d l ti l if density it of metal/oxide over ~100um diameter – Metal density rule to avoid large area without metal dummy metal fill d t l – Limit the width of metal to avoid large area with only metal metal slot rules D.Su & B. Murmann EE315A ― HO #20 12 Dummy Metal Fill • Automatic generation of small rectangles in “empty” space to provide more uniform density • Dummy metal can impact parasitic capacitance. capacitance • Can block the automatic generation of dummy metal ( ith a d d t l (with dummy bl k l block layer) ) for critical circuits D.Su & B. Murmann EE315A ― HO #20 13 Wide Metal • Metal width can not be too wide –C Copper i softer than oxide. is f h id – CMP can over polish the copper, reducing its thickness (increasing resistance) and making thi k (i i i t ) d ki the overall surface less planar (more difficult for higher layer metal) • Add slots to metal width to increase the density of oxide – Or, avoid using very wide metal, use several narrower metal lines in parallel D.Su & B. Murmann EE315A ― HO #20 14 Matching • A major advantage of VLSI design is device matching: – Fully differential circuits CMRR, offset – Current mirrors – Ratioed devices: capacitors, resistors, transistors • Random mismatch: – Process: geometry, implant dose, … • Systematic: – M k gradient Mask di t – Thermal gradient EE315A ― HO #20 D.Su & B. Murmann 15 Systematic vs Random Mismatch Dis stribution of Parame eter μ Systematic S t ti Random σ −3σ −2σ −σ σ 2σ 3σ • Systematic mismatch changes the average y g g • Random mismatch leads to fluctuation/spread D.Su & B. Murmann EE315A ― HO #20 16 Intrinsic Resistor • Ohms/square, R ; voltage coefficient • Types: – Poly (salicided vs non-salicided) y( ) – Diffusion (salicided vs non-salicided) – Nwell for kohm/square R intrinsic ⎛L⎞ = # of Squares ⎜ ⎟ × R ⎝W⎠ EE315A ― HO #20 D.Su & B. Murmann 17 Poly Resistor 1 Metal 1 L contact Poly W Salicide Block • Types (consult design/electric rules) – – – – p or n doped salicided or non salicided non-salicided Recommended width > minimum poly width Choice: R , voltage coefficient, matching D.Su & B. Murmann EE315A ― HO #20 18 Poly Resistor 2 Metal 1 L contact Poly W Salicide Block • Resistance = 2 X Rend + Rintrinsic • Keep W large to reduce Rend • Keep L large to reduce voltage dependency EE315A ― HO #20 D.Su & B. Murmann 19 Resistor Matching • Systematic Mismatch – Use identical unit elements – Keep same orientation, environment • Use dummy resistors • Minimize metal routing over resistors (keep all metal routing identical) to reduce noise coupling – Watch out for mask gradient, temperature gradient, pressure gradient • Keep devices in close proximity • Use interdigitated layout • Random Mismatch – Keep W and L large to reduce random mismatch – Reduce the contribution of Rend D.Su & B. Murmann EE315A ― HO #20 20 Interdigitated Resistor Layout +Δ +2Δ +3Δ +4Δ +5Δ RA RB RA RA RB RA Dum mmy Dum mmy 0 Top View • I t di it t d ABAABA Interdigitated: • Remove linear gradient in temperature, mask CD, pressure EE315A ― HO #20 D.Su & B. Murmann 21 Capacitor • Metal sandwich capacitor – Small fF/um^2 fF/um 2 • MiM: Metal-insulator-Metal (process option) – 1-2 fF/um^2 – Best matching • Interdigitated metal capacitor – Standard process – Almost as high density as standard MiM – Matching is not as good as MiM • MOS capacitors OS – High density – Poor voltage coefficient D.Su & B. Murmann EE315A ― HO #20 22 Intrinsic Capacitor Top Bottom Cross Section • Assume no fringing effect CINT = ε Area tox EE315A ― HO #20 D.Su & B. Murmann 23 Sandwich Capacitor M6 Top Bottom M5 M4 CINT Top CBOT CTOP M3 M2 Capacitor Model Bottom Cross Section D.Su & B. Murmann EE315A ― HO #20 24 Interdigitated Capacitor M6 + - + - + M5 - + - + - M4 + - + - + M3 - + - + - M2 + - + - + • Alternating fingers of it capacitors • Vertical separation is larger than horizontal g separation; most capacitance from lateral flux • Other permutations are possible (see references) Cross-section H. Samavati, et al, “Fractal Capacitors,” JSSC, Dec 1998. R. Aparicio, A. Hajimir, “Capacity li it & matching properties of i t R A i i A H ji i “C it limits t hi ti f integrated capacitors, JSSC March 2002. t d it JSSC, M h 2002 EE315A ― HO #20 D.Su & B. Murmann 25 Capacitor Matching • Systematic Mismatch – Use identical unit elements in an array – Keep same environment • U d Use dummy capacitors it – Watch out for mask, temperature, pressure gradient • Keep devices in close p p proximity y • Use common centroid layout – Keep routing parasitics small and matched • Random Mismatch – Use large area to reduce random mismatch D.Su & B. Murmann EE315A ― HO #20 26 Common Centroid Capacitor C1 C2 C2 C1 Top View D.Su & B. Murmann EE315A ― HO #20 27 MOS Transistors • Layout • Random Mismatch – Process tolerance Large W and L – Vt, beta keep Vgs-Vt large • Systematic Mismatch – Gradient: Common centroid layout – Implant angle: Step symmetry vs mirror symmetry t – Neighbor effect: add dummies D.Su & B. Murmann EE315A ― HO #20 28 NMOS Transistor Cross-Section Metal 1 source drain gate STI n+ n+ p STI EE315A ― HO #20 D.Su & B. Murmann 29 NMOS Transistor Top View gate drain source contact Metal 1 W N diff N-diff Poly L D.Su & B. Murmann EE315A ― HO #20 30 PMOS Transistor Top View gate drain d i source contact Metal 1 W P-diff Poly L Nwell EE315A ― HO #20 D.Su & B. Murmann 31 Gate Resistance • Gate resistance: –K Keep W short h t – Connect on one end: Rg = 1/3 x (W/L) x R – Connect on both ends: Rg = 1/12 x (W/L) x R Rg Ref: Razavi et al, “Impact of distributed gate resistance on the performance of MOS devices ” al Impact devices, IEEE Trans circuits & systems I, Nov 1994. D.Su & B. Murmann EE315A ― HO #20 32 Random Transistor Mismatch ID = ID = 1 W μCox (VGS − VT ) 2 2 L β 2 (VGS − VT ) 2 Random Mismatch in: 2 σ ΔI D / ID = VT and β 2 4σ ΔVt (VGS − VT ) 2 2 + σ Δβ / β Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989. EE315A ― HO #20 D.Su & B. Murmann 33 Distr ribution of VT Random Threshold Mismatch Random σ −3σ −2σ −σ σ ΔV ≈ t AVT W ×L Ignoring distance effect σ 2σ 3σ AVT = 3 – 10 mV μm Process Dependent Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989. D.Su & B. Murmann EE315A ― HO #20 34 Example: Threshold Mismatch V1 50 / 1 v2 50 / 1 If AVT = 5mVμm σ Δ (V 1−V 2) ≈ AVT 5mVμm = = 0.71mV W ×L 50μm ×1μm Ignoring distance effect Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989. D.Su & B. Murmann EE315A ― HO #20 35 β Mismatch σΔ Δβ / β ≈ Aβ W ×L Ignoring distance effect Aβ ≈ 0 5 - 3 % 0.5 D.Su & B. Murmann EE315A ― HO #20 36 Vt Matching Data 90nm data [Chang, Trans. Electron Devices, 7/2005] AVT~tox [Pelgrom, IEDM 1998] EE315A ― HO #20 D.Su & B. Murmann 37 Mirror Inaccuracy Due to Mismatch ΔI = I1 − I 2 ≅ − g m ΔVt + I1 Δβ g ΔI Δβ ≅ − m ΔVt + I1 I1 β 2 σ ΔI ≅ I1 • gm 2 2 σ ΔVt + σ Δβ I1 β Example: W=10μm, L=0.35μm, gm/ID=10S/A, AVT = 7mV/um, Aβ=1% ⎛ ⎝ σ ΔI = ⎜ 10 I1 • β 2 S ⎞ ⋅ 3.7 mV ⎟ + (0.53% )2 = A ⎠ (3.7% )2 + (0.53% )2 = 3.74% Threshold mismatch usually dominates D.Su & B. Murmann EE315A ― HO #20 38 Systematic Mismatch • Gradient: Thermal, Mask, Pressure – Common centroid layout • Implant angle: Step symmetry vs mirror y y symmetry • Neighbor effect: add dummies D.Su & B. Murmann EE315A ― HO #20 39 Gradient Cancellation • Gradient: Thermal, Mask, Pressure • Linear gradient is easy to cancel – Common centroid layout y • Other techniques exist for higher order gradient cancellation – Ref: G. Van der Plas, et al, JSSC, Dec 1999 D.Su & B. Murmann EE315A ― HO #20 40 Implant Angle n+ STI p n+ STI • A small angle of 7 deg in implant results in slight different in implant; modern processes will compensate for this but ... • Keep same orientation/direction of current for matched devices – Step symmetry vs mirror symmetry EE315A ― HO #20 D.Su & B. Murmann 41 Step vs Mirror Symmetry M1 M2 Step Symmetry S D S D S D D S Mirror Symmetry Not preferred M2 M1 D.Su & B. Murmann EE315A ― HO #20 42 Common Centroid Transistors 1 M1 M2 S D D S S D D S M1 M2 Cancellation of offset due to current flow direction EE315A ― HO #20 D.Su & B. Murmann 43 Common Centroid Transistors 2 D D M1 M2 S S D D M2 M1 S S Same current flow direction D.Su & B. Murmann EE315A ― HO #20 44 Differential Pair Dummy D2 D1 M1 M1 M2 SS M1 M2 M2 Dummy D D.Su & B. Murmann Dummy SS SS D1 D2 SS SS D2 D1 SS SS M2 M2 M1 M1 Dummy D EE315A ― HO #20 45 Neighbor Effects • Keep the “neighborhood” of matched transistors identical y g • Add dummy transistors for the “edged” devices z direction • Watch out for z-direction as well – Metal layers must also match – Avoid Metal-1 overlap D.Su & B. Murmann EE315A ― HO #20 46 Second order effects • Second order effects of MOS transistors – Antenna rule – Strained silicon – Well proximity D.Su & B. Murmann EE315A ― HO #20 47 Antenna Rule • Implant/deposition process can induce charge on metal and create voltage stress on gate capacitance • Q=CV; If C is small, V is large Damage! Large VT shift – Q depends on area (Copper) and perimeter (Aluminum) of metal – C depends on the W x L ( d d th (area) of th t ) f the transistor gate i t t V ∝ Metal - Gate Ratio = Area/Perimeter of Metal Gate area of transistor • “Antenna rule” violation when induced voltage V exceeds safe limits. • Solution: Add “antenna” (reverse-biased) diodes to shunt charge D.Su & B. Murmann EE315A ― HO #20 48 Length of Diffusion ( g (LOD) Effect ) SA SD SB Shallow S Trench Isolation Edge Source: Sally Liu, ISSCC 2006 SET • • • • STI (shallow trench isolation) induces mechanical stress effect on transistor strained device Starting with 130nm/90nm and modulated by the distance between poly and OD/STI edge (SA SB) (SA, Applies to both NMOS and PMOS (see DRC) Effect can be extracted in Layout Parasitic Extraction (LPE) simulations. i l ti D.Su & B. Murmann EE315A ― HO #20 49 Minimizing LOD Effect Different SB • Use unit devices for best matching • Avoid using irregular diffusion shape • Use dummy transistors on both ends of a multi-finger device to keep the same SA and SB for matching D.Su & B. Murmann EE315A ― HO #20 50 Well Edge Proximity Effect 1 Shallow Trench Isolation (STI) YM Y-M Sheu et al, CICC 2005 al D.Su & B. Murmann • Well proximity ions scatter at well photo resist edge, bounce into the active region and thus increase the device threshold voltage • Affects device matching • Important for Well to gate spacing: SC of 1um or less • Should be modeled by LPE extraction • Well proximity effect reduced by guard ring EE315A ― HO #20 51 Well Edge Proximity Effect 2 • P. G P G. Drennan et al., "Implications of Proximity Effects for Analog Design " Proc CICC, pp.169 al Implications Design, Proc. CICC pp 169176, Sep. 2006. D.Su & B. Murmann EE315A ― HO #20 52 Minimizing WPE Effect Matched Keep SC large g NWELL • Keep distance between gate to well as large as possible (>> 1um; see DRC) • For matching, keep SC equal and large matching D.Su & B. Murmann EE315A ― HO #20 53 Transistor Matching • Keep transistor area large • Use same size, shape, orientation, and in close proximity • Keep same voltage, current, temperature • Minimize gradient effect: common centroid g • Keep neighbors (up to >10um) identical in , x, y, and z directions – Use dummy devices – Avoid edge of chip g p D.Su & B. Murmann EE315A ― HO #20 54 ...
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This note was uploaded on 08/13/2009 for the course EE 315 taught by Professor Borismurmann during the Spring '09 term at Stanford.

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