Lecture 01 - Introduction

Lecture 01 - Introduction - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Introduction Session 01 Session 01
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2 3 Testing Source: IEEE Spectrum 4 Test Philosophy A Pass/Fail test: 70% Pass Quality Prob(PQ) = 0.7 30% Fail Quality Prob(PF) = 0.3 All Students Prob(P|PQ) = 0.95 Prob(F|FQ) = 0.95 P ro b (P |F Q ) = 0 .0 5 (F |P ? % Passed ? % Failed PQ: student is pass quality PF: student is fail quality P: student passes the test F: student is fail quality
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3 5 Test Philosophy (cont’d) Probability of passing: Student risk: 11% of failed students should have passed 68 . 0 30 . 0 05 . 0 70 . 0 95 . 0 ) ( ) | ( ) ( ) | ( ) ( = + = + = FQ Prob FQ P Prob PQ Prob PQ P Prob P Prob 11 . 0 32 . 0 7 . 0 05 . 0 ) ( Prob ) ( Prob ) | ( Prob ) | ( Prob = = = F PQ PQ F F PQ 6 Test Philosophy (cont’d) Student’s risk (manufacturer’s risk or yield loss ): Teacher’s risk (consumer’s risk): 11 . 0 32 . 0 7 . 0 05 . 0 ) ( Prob ) ( Prob ) | ( Prob ) | ( Prob = = = F PQ PQ F F PQ 022 . 0 68 . 0 3 . 0 05 . 0 ) ( Prob ) ( Prob ) | ( Prob ) | ( Prob = = = P FQ FQ P P FQ
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4 7 VLSI Chips – Present and Future 2.8 – 109 2 – 96 1.2 – 61 Power, W 0.5 – 0.9 0.9 – 1.5 1.2 – 2.5 Voltage, V 840 – 1830 530 – 1100 200 – 730 Clock Rate, MHz 260 – 2690 160 – 1475 100 – 900 Pin count 70 – 750 60 – 520 50 – 385 Die Size, mm 2 8 – 9 7 – 8 6 – 7 Number of wiring layers 84 – 180 18 – 39 4 – 10 Millions of Transistors/cm 2 0.07 – 0.05 0.13 – 0.10 0.25 – 0.15 Feature Size, μm 2009-2012 2003-2006 1997-2001 Year 8 VLSI Fabrication Process A seed crystal is dipped into the melted silicon to initiate single- crystal growth Diameter: 75 – 230 mm Growth rate: 30 – 180 mm/hour The output is a silicon ingot Using diamond blades, the wafers are produces (thickness = 0.25 – 1 mm) At least one surface is polished to a flat, scratch-free mirror finish
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5 9 VLSI Fabrication Process (cont’d) 10 What May Go Wrong? Shorts between two points (bridges) Open in a line Improper doping Masking error Improper thickness of a line Particles on surface Electron migration due to heat Corrosion
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6 11 What Can be Done? 1. Wafer probe testing. 2. Use microscope to find faulty dices. Mark with a small ink. Reject after separation. Package the unmarked dies. 3. Test for electrical and mechanical characteristics.
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Lecture 01 - Introduction - Testing and Testable Design...

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