Lecture 02 - Fault Modeling

Lecture 02 - Fault Modeling - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Fault Modeling Session 02 Session 02
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2 3 Goals of Fault Modeling To model physical defects in the circuit at high level of abstraction. To allow test generation and fault/coverage analysis to be done early in the design process. To model high percentage of the actual physical defects that can occur in components: To reduce number of individual defects that have to be considered (e.g. find equivalent or dominant faults). To reduce the complexity of the component/circuit description for test generation/analysis. 4 Stuck-at Fault Model Most commonly used fault model. May consider “single” or “multiple” stuck-at faults. The components are assumed to be (internally) fault-free. The effect of faults is modeled by having a line segment tied to either: Vcc (s-a-1) GND (s-a-0)
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3 5 Stuck-at Fault Model (cont’d) Example: Fault-free function: f = x 1 x 2 + x 2 x 3 Faulty functions: Fault 1/0 Æ f* = x 2 x 3 Fault 2/1 Æ f* = x 1 + x 3 Fault 6/0 Æ f* = x 2 x 3 Line Segment Stuck-at Value 6 Features of Single s-a-f Model Can be applied at the logic/RTL/system levels. Reasonable and manageable number of faults (i.e. less or equal 2 * # of line segments 2 * # of circuit nodes). So, is computationally feasible to deal with. Well-developed algorithms exist for automatic test patter generation (ATPG) Other useful fault models like stuck-open, bridging, etc. can be applied into (sequence of) stuck-at faults
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4 7 Features of Single s-a-f Model (cont’d) Empirical evidence shows that single stuck-at fault model covers the majority (about 90%) of the possible manufacturing defects in circuits such as: Source-drain shorts Oxide pinholes Diffusion contaminants Metallization shorts 8 Stuck-Open Fault Model The main assumption in this model is that a single physical line in the circuit is broken (usually internal to gates). In CMOS circuit, a broken line may result in a “memory effect”. Example: A CMOS NOR gate
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5 9 Stuck-Open Fault Model (cont’d) Detecting faults at l2 or l3: 0 0 0 0 on on off off 1 1 f old f old 0 0 off on on off 0 1 0 0 0 0 on off off on 1 0 1 1 f old 1 off off on on 0 0 at l3 at l2 at l1 Stuck-Open f T4 T3 T2 T1 B A f old=1 on off off on 1 0 1 off off on on 0 0 f T4 T3 T2 T1 B A Since there is not a path from either Vdd or Vss to the output, f retain the previous value for some undetermined discharge time 10
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Lecture 02 - Fault Modeling - Testing and Testable Design...

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