Lecture 03 - Fault Simulation - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Fault Simulation Session 03 Session 03
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2 3 Fault Analysis System (Review) Fault Collapsing Test Generation Fault Simulation 4 Logic Simulation
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3 5 Logic Simulation Logic simulation for a combinational logic circuit is the determination of steady-state logic values implied at each circuit line by the vector applied to its primary inputs Two-valued logic simulation: When each component of the vector applied P = ( p 1 , p 2 ,… p n ) is fully-specified, i.e., can take only two values – 0 and 1 Three-valued logic simulation: When one or more component of vector applied is incompletely specified, i.e., has the value x There are 5, 7, 9, even 41-level logic simulation where more detailed information is processed and provided. 6 Logic Simulation (cont’d) Such simulators implicitly assume that the details of delays are unimportant in determining the steady state values implied by this vector Are hence called cycle-based or zero delay simulators If used to verify correctness of a circuit design, such simulation must be complemented by timing analysis A simple logic simulator must Read vector to be simulated and assign the values to corresponding inputs Compute the value implied by the vector at each circuit line
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4 7 Logic Simulation (cont’d) However, the value at a line must be computed after the values at all its fanins are computed E.g., value at c 7 must be computed after those at both its fan-ins, x 2 and c 5 , are computed & & & & & & x 1 x 2 x 3 x 4 x 5 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 G 1 G 2 G 3 G 4 G 5 G 6 z 1 z 2 8 Level-Based Logic Simulation For combinational circuits, lines can be ordered a priori to ensure correct logic simulation Input level of line c i in a combinational circuit, η inp ( c i ), is the maximum number of circuit elements traversed along any path from any of the circuit inputs to the line Circuit lines can then be considered during simulation in non-decreasing order in terms of the values of their input levels
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5 9 Level-Based Logic Simulation (cont’d) Procedure InputLevelize() can compute η inp ( c i ) for all lines Note that Step 3 of above procedure can be implemented more efficiently 10 Level-Based Logic Simulation (cont’d) Once η is computed for each line, the lines can be sorted in ascending order of their η values in an ordered list Q η . Example of computing η : & & & & & & 0 0 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 x 1 x 2 x 3 x 4 x 5 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 G 1 G 2 G 3 G 4 G 5 G 6 z 1 z 2
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6 11 Level-Based Logic Simulation (cont’d) Once the η inp values are computed, the lines can be ordered as Q η =( x 1 , x 2 , x 3 , x 4 , x 5 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 2 , z 1 , z 2 ) Note that Q η is not unique in this case Circuit lines can be considered in the sequence given by Q η during logic simulation & & & & & & 0 0 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 x 1 x 2 x 3 x 4 x 5 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 G
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Lecture 03 - Fault Simulation - Testing and Testable Design...

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