Lecture 05 - Test Generation Sequential

Lecture 05 - Test Generation Sequential - 1 1 Testing and...

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Unformatted text preview: 1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Test Generation for Sequential Circuits Session 05 Session 05 2 3 Main Concept & Strategy 4 Sequential Circuits • A sequential circuit has memory (e.g. flip-flops) in addition to combinational logic. — As the combinational part is much larger than the memory/feedback part, most approaches (e.g. DFT techniques) deal only with the combinational part. • Test for a fault in a sequential circuit is a sequence of vectors, which – Initializes the circuit to a known state – Activates the fault, and – Propagates the fault effect to a primary output • Methods of sequential circuit ATPG – Time-frame expansion methods – Simulation-based methods 3 5 Taxonomy 6 Concept of Time-Frames • Most sequential test generation techniques are based on a combinational iterative array model — Feedback signals are generated from the copies of the combinational logic in the previous time frames — A clock pulse is applied between each pair of successive time frames to update the logic values — A single s-a-f corresponds to the fault in all time frames 4 7 Concept of Time-Frames (cont.) • If the effect of fault f does not propagate to the next- state line in a particular time frame, then the faulty and fault-free values of the corresponding present-state lines are the same in those time frames. • A single event fault at one time frame may become a multiple-event fault in another time frame. Single-event fault Multiple-event fault Present State Lines Next State Lines 8 Concept of Time-Frames (cont.) • If the test sequence for a single stuck-at fault contains n vectors, – Replicate combinational logic block n times – Place fault in each block – Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame Time- frame-1 Time- frame- n +1 Unknown or given Init. state Vector 0 Vector -1 Vector - n +1 PO 0 PO -1 PO - n +1 State variables Next state 5 9 Extended D-Algorithm • Start with time frame 0 and use the D-algorithm to generate a test vector for this time frame — If the error propagates to at least one primary output in time frame 0, it’s done (test vector is found) — If the error propagates only to the next-state lines, a new time frame is added as the next time frame to further propagate the error. This process continues until the error reaches at least one of the primary outputs....
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Lecture 05 - Test Generation Sequential - 1 1 Testing and...

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