Lecture 06 - Path Delay Fault Test

Lecture 06 - Path Delay Fault Test - Testing and Testable...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Path Delay Testing Session 06 Session 06
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2 3 4 Delay test definition Circuit delays and event propagation Path-delay tests ± Non-robust test ± Robust test ± Five-valued logic and test generation Path-delay fault (PDF) and other fault models Test application methods ± Combinational, enhanced-scan and normal-scan ± Variable-clock and rated-clock methods Advanced Techniques Key Issues
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3 5 Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing . For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. Delay test problem for asynchronous circuits is complex and not well understood. 6 Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized With clock Digital Circuit Timing
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4 7 Switching or inertial delay is the interval between input change and output change of a gate: ± Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. ± Also depends on input rise or fall times and states of other inputs (second-order effects). ± Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. Propagation or interconnect delay is the time a transition takes to travel between gates: ± Depends on transmission line effects (distributed R , L , C parameters, length and loading) of routing paths. ± Approximation: modeled as lumped delays for gate inputs. See next slide for some timing models. Circuit Delays 8 b a c (CMOS) Time units 0 5 (zero delay) (unit delay) (multiple delay) (min-max delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X Options for Inertial Delay (e.g. NAND)
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5 9 2 4 6 1 1 3 5 3 1 0 0 0 2 2 Path P1 P2 P3 Event Propagation Delays Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew 10 Circuit Outputs Initial value=0 Initial value=0 Final value=1 Final value=0 Clock period Fast transitions Slow transitions time Each path can potentially produce one signal transition at the output. The location of an output transition in time is determined by the delay of the path. Fast transitions: transitions with delay <= T ck Slow transitions: transitions with delay > T ck If delay of a path increases/decreases, the corresponding output transitions move to right/left.
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6 11 Slow-Fast Clocking Scheme Using slow clock for state justification and error propagation ensures that they are not invalidated by other delay faults.
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Lecture 06 - Path Delay Fault Test - Testing and Testable...

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