Lecture 07 - Memoy Test 01 - 1 1 Testing and Testable...

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Unformatted text preview: 1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Memory Testing Session 07 Session 07 2 3 Key Issues • Motivation for testing memories • Modeling memory chips • Reduced functional fault models • Traditional tests • March tests • Pseudorandom memory tests 4 Motivation for Memory Testing 3 5 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 99 02 05 08 11 14 Memory Logic-Reused Logic-New % of chip area year • Memories dominate chip area (94% of chip area in 2014) • Memories are most defect sensitive parts — Because they are fabricated with minimal feature widths • Memories have a large impact on total chip DPM level — Therefore high quality tests required • (Self) Repair becoming standard for larger memories (> 1 Mbit) Importance of Memories 6 Memory Chip Trend (Density and Capacity) • 1970 -- DRAM Invention (Intel) 1024 bits • 1993 -- 1st 256 MBit DRAM papers • 1997 -- 1st 256 MBit DRAM samples — 1c/bit --> 120 X 10-6 c/bit 4 7 Typical RAM Production Flow Wafer Wafer Full Probe Test Marking Final Test Shipping QA Sample Test Visual Inspection Burn-In (BI) Post-BI Test Laser Repair Packaging Pre-BI Test 8 Dollars per DRAM chip Price of high-volume parts is constant in time; except for inflation Note : Slope of line matches inflation! Memory Chip Cost Over Time • DRAM Price per Bit — 1991: US$ 400 / Mega bits — 1995: US$ 3.75 / Mega bits — 1999: US$ 0.1~0.3 / Mega bits 5 9 Algorithm complexity (Cycle time = 150 ns) n Number of bits O( n ) O( n *log 2 n ) O( n 3/2 ) O( n 2 ) 1 K 0.0001 s 0.001 s 0.003 s 0.1 s 1 M 0.1 s 2.1 s 110 s 30.6 h 4 M 0.42 s 9.2 s 860 s 20.3 d 16 M 1.68 s 40.3 s 1.91 h 325 d 64 M 6.71 s 174 s 15.3 h 14.2 y 256 M 26.8 s 2.09 h 122 h 228 y 1 G 107 s 8.94 h 977 h 3655 y Complexity of Memory Test • A memory is tested with several algorithms , which together may go through the total address space over 100 times • Effective test time for 16 Mb DRAM, using O( n ) tests, is about 168s — Test time reduced using on-chip parallelism (DFT and BIST) 10 Fault Types (Review) • Fault types: — Permanent-- System is broken and stays broken the same way indefinitely — Transient-- Fault temporarily affects the system behavior, and then the system reverts to the good machine -- time dependency, caused by environmental condition — Intermittent-- Sometimes causes a failure, sometimes does not 6 11 Fault Types (cont.) • Permanent faults: — Missing/Added Electrical Connection — Broken Component (IC mask defect or silicon-to-metal connection) — Burnt-out Chip Wire — Corroded connection between chip & package — Chip logic error (Pentium division bug) • Transient Faults: — Cosmic Ray — An α particle (ionized Helium atom) — Air pollution (causes wire short/open) — Humidity (temporary short) — Temperature (temporary logic error) — Pressure (temporary wire open/short) — Vibration (temporary wire open) — Power Supply Fluctuation (logic error)...
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Lecture 07 - Memoy Test 01 - 1 1 Testing and Testable...

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