Lecture 08 - Scan 03 - Testing and Testable Design...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Scan Design for Testability Session 08 Session 08
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 3 Boundary Scan for Advanced Networks – IEEE 1149.6 4 Rationale Analog test receiver Digital driver logic Digital receiver logic Test access port for 1149.6 Key Issues
Background image of page 2
3 5 Rationale Advanced signaling techniques are required for multiple-giga-per-second serial I/O. Differential AC-coupled networks Coupling capacitor in AC-coupled networks blocks DC signals. DC-level applied during EXTEST may decay to undefined logic level. 6 C U TX RX C U V T TX RX Update-DR Capture-DR V H V L V H V L Capturing AC-Coupled Signal with 1149.1 Capture logic (R1 FF in BSC) Update logic (R2 FF in BSC)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 7 C U TX RX C U Configuration for Differential Signaling Two ways to deal with differential networks Place BSC on both outputs of the driver and both inputs of the receiver ( not practical due to the fault- tolerant nature of differential receivers). Place a single BSC attached internally to the driver and another BSC internally to the receiver. 8 Analog Test Receiver It uses a self-referenced comparator along with voltage and delay hysteresis to capture a valid edge and filter any unwanted noise. The receiver uses a low-pass filter to create a delayed reference signal.
Background image of page 4
5 9 Digital Driver Logic 0 1 0 1 C U ShiftDR Shift in ClockDR UpdateDR Mode Shift out Data Mission 0 1 AC Mode TCK RTI State AC Test Signal (distributed to all AC drivers) Train/Pulse Mode AC Mode Train/Pulse 1149.1 Bypass 1149.1 Extest Extest_Pulse Extest_Train 0X X 10 X 11 0 11 1 AC Test Signal Generator (near TAP Controller) AC Test Signal Insertion, per driver D Q The driver is required to drive a pulse (or pulses) when it is executing EXTEST_PULSE or EXTEST_TRAIN instructions. 10 Digital Driver Logic (cont.) RTI State signal is driven by TAP controller when it is in Run-Test/Idle state while executing EXTEST_PULSE and EXTEST_TRAIN instructions EXTEST_PULSE Drive the signal to the opposite state Wait for the signal to fully decay Drive the signal to the correct value (to get captured) EXTEST_TRAIN Generate a continuous waveform based on TCK This allows TCK frequency to be adjusted to allow maximum decay for the driver side without affecting the receiver side
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 11 Digital Receiver Logic V Hyst V Hyst Pad R F C F V T DC AC EXTEST_PULSE or EXTEST_TRAIN Selected Hyst Mem Clear Set Shift In Init_Memory (common to all test receivers) Capture FF Update ClockDR 0 1 ShiftDR Shift Out UpdateDR 0 1 Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only Boundary Register Cell Test Receiver D EXTEST_PULSE, EXTEST_TRAIN: Latch Q NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only. TCK Capture-DR Shift_DR TAP State TMS
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

Page1 / 23

Lecture 08 - Scan 03 - Testing and Testable Design...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online