Lecture 09 - BIST 01

Lecture 09 - BIST 01 - 1 1 Testing and Testable Design...

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Unformatted text preview: 1 1 Testing and Testable Design Testing and Testable Design `x{wtw at| Dept. of EE Univ. of Texas at Dallas 2 Built-In Self-Test (BIST) Session 09 Session 09 2 3 Basic Concept 4 Key Issues Motivation and economics Definitions for components and procedures Built-in self-testing (BIST) process BIST pattern generation (PG) BIST response compaction (RC) Aliasing probability 3 5 Motivation The problems in todays semiconductor testing Traditional test techniques become quite expensive No longer provide sufficiently high fault coverage Why do we need built-in self-test (BIST)? For mission-critical applications Detect un-modeled faults Provide remote diagnosis Useful for field test and diagnosis (less expensive than a ATE) Software tests for field test and diagnosis: Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis 6 Motivation (cont.) Costly test problems can be alleviated by BIST Increasing chip logic-to-pin ratio harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for above 1 GHz clocking chips Hard testability insertion designers unfamiliar with gate-level logic, since they design at behavioral level In-circuit testing no longer technically feasible Shortage of test engineers Circuit testing cannot be easily partitioned 4 7 BIST Concept Built-in self-test refers to techniques and circuit configurations that enable a chip to test itself In this methodology, test patterns are generated and test responses are analyzed on- chip. The simplest of BIST designs has a pattern generator (PG) and a response analyzer (RA) 8 BIST Advantages BIST offers several advantages over testing using automatic test equipment (ATE) 1. In BIST the test circuitry is incorporated on-chip and no external tester is required (especially attractive for high-speed circuits). 2. Self-test can be performed at the circuit's normal clock rate. 3. Self-testable chip has the ability to perform self-test even after it is incorporated into a system (either for periodic testing or to diagnose system failures). 5 9 Main BIST Techniques Logic BIST Techniques 1. Online BIST Concurrent online BIST Non Concurrent online BIST 2. Offline BIST Functional offline BIST Structural offline BIST A typical logic BIST system Non- concurrent BIST Offline Online Concurrent Functional Structural [Abramovici 1994] Logic BIST Controller Test Pattern Generator (TPG) Output Response Analyzer (ORA) Circuit Under Test (CUT) 10 Economics BIST Costs Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter...
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Lecture 09 - BIST 01 - 1 1 Testing and Testable Design...

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