Lecture 09 - BIST 02

# Lecture 09 - BIST 02 - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Built-In Self-Test (BIST) Session 09 Session 09

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2 3 Various LFSR Architectures 4 Exhaustive-Pattern LFSR Binary counter can be used to generate all 2 n patterns Example: 4-bit binary counter X 1 X 3 X 4 X 2
3 5 Complete LFSR We can easily modify the LFSR to generate the complete sequence that includes all-zero pattern When LFSR has 0…001, the output of NOR is 1 and the last XOR injects a 0 . So, the next state will be all zero 0…000. When LFSR has 0…000, the output of NOR is 1 again but the last XOR injects a 1. So, the next state will be out of all-zero state. 6 Examples of Complete LFSR Further optimization would be possible by optimizing NOR and XOR gates together. 00 01 0 0 0 1 10 0 0 (a) 4-stage standard CFSR (b) 4-stage modular CFSR (c) A minimized version of (a) (d) A minimized version of (b)

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4 7 Reverse-Order Sequence In some test scenarios, a pair of test sequences are required where one contains vectors in the reverse order of the other. The reverse-order sequence can be generated using polynomial: φ ( x )=x n φ (1/ ) Example: 5-statge internal XOR LFSR with —(a) φ ( )=x 5 +x 2 +1 (b) φ ( )=x 5 +x3+1 8 Hybrid LFSR Polynomial f(x)=1+b(x)+c(x) is fully decomposable iff both b(x) and c(x) have no common terms and there exists an integer j such that c(x)=x j b(x), j>=1 If f(x) is fully decomposable, then we have f(x)=1+b(x)+x j b(x) A hybrid (top-bottom) LFSR can be constructed using polynomial s(x)=1+^x j +x The term ^x j indicates the XOR gate with one input is connected to the feedback path, not between stages
5 9 When number of stages n is and odd number, it can be realized using (n+1)/2 XORs. Details in: L. Wang and E. McCluskey, “Hybrid Design Generating Maximum-Length Sequences,”, Trans. CAD, 1988. (a) 5-stage top-bottom LFSR (b) 5-stage bottom-top LFSR 5-Stage Hybrid LFSRs D0 D1 D2 D3 D4 D0 D1 D2 D3 D4 Internal XOR part: φ ( x )=1+x 4 +x5 Internal XOR part: φ ( )=1+x 2 +x5 10 Consider an AND gate with large fan-in: If p (1) at all PIs is 0.5, F (1) = 0.5 8 = 1/256 and (0) = 1-(1/256) = 255/256 Will need enormous # of random patterns to test a stuck- at 0 fault on F -- LFSR (1) = 0.5 We must not use an ordinary LFSR to test this IBM – holds patents on weighted pseudo-random pattern generator in ATE s-a-0 Weighted Pseudo-Random Pattern

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6 11 For a regular LFSR p (1) = 0.5 Solution to get a weighted LFSR Add programmable weight selection and complement LFSR bits to get p (1)’s other than 0.5 Need 2-3 weight sets for a typical circuit Weighted pattern generator drastically shortens pattern length for pseudo-random patterns Weighted LFSR 12 w 1 0 0 0 0 2 0 0 1 1 Inv . 0
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Lecture 09 - BIST 02 - Testing and Testable Design...

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