Lecture 09 - BIST 03 - Testing and Testable Design...

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1 1 Testing and Testable Design Testing and Testable Design `x{Üwtw aÉâÜtÇ| Dept. of EE Univ. of Texas at Dallas 2 Built-In Self-Test (BIST) Session 09 Session 09
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2 3 Logic BIST Architectures 4 Logic BIST Architectures Without Scan Chains Centralized and Separate board-level BIST (CSBL) Built-In Evaluation and Self-Test (BEST) With Scan Chains ( test-per-scan ) LSSD on-chip self-test (LOCST) Self-testing using MISR and parallel SRSG (STUMPS) Using Register Reconfiguration ( test-per-clock ) Built-In Logic Block Observer (BILBO) Modified BILBO (MBILBO) Concurrent BILBO (CBILBO) Circular self-test path (CSTP) Using Concurrent Checking Circuit Concurrent self verification (CSV)
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3 5 Centralized and Separate Board-Level BIST (CSBL) Two LFSRs and two multiplexers are added to the circuit. The first LFSR acts as a PRPG, the second serves as a SISR. The first multiplexer selects the inputs, another routes the PO to the SISR. PIs CUT (C or S) MUX SISR k 1 m M U X n 1 k = [log 2 m ] PRPG n TEST 6 Built-In Evaluation and Self-Test (BEST) Use a PRPG and a MISR. Pseudo-random patterns are applied in parallel from the PRPG to the chip primary inputs (PIs) An MISR is used to compact the chip output responses CUT (C or S) M I S R P R P G PIs
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4 7 LSSD On-chip Self-Test (LOCST) In addition to the internal scan chain, an external scan chain comprising all primary inputs and primary outputs is required. The external scan-chain input is connected to the scan-out point of the internal scan chain. S in CUT (C) S i S o POs PIs SRL R 2 SISR PRPG S out SRL R 1 8 Self-testing using MISR and parallel SRSG (STUMPS) The only BIST architecture widely used in industry. Contains a PRPG (SRSG) and a MISR. The scan chains are loaded in parallel from the PRPG. The system clocks are then pulsed and the test responses are scanned out to the MISR for compaction. New test patterns are scanned in at the same time when the test responses are being scanned out. PRPG MISR CUT (C or S) CUT (C or S) Linear Phase Compactor MISR Linear Phase Shifter PRPG A STUMPS-based Architecture STUMPS
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5 9 Built-In Logic Block Observer (BILBO) Complex systems with multiple chips demand elaborate logic BIST architectures BILBO and test / clock system Shorter test length, more BIST hardware Combined functionality of D flip-flop, pattern generator , response compacter , & scan chain Reset all FFs to 0 by scanning in zeros 10 Example BILBO Usage SI Scan In SO Scan Out Characteristic polynomial : 1 + x + … + n CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR CUT B: BILBO1 is LFSR, BILBO2 is MISR
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6 11 1. Serial Scan Mode - B 1 2 = “00” 2. LFSR Pattern Generator Mode - 1 2 = “01” BILBO Modes 12 3. D-FF Normal Mode - 1 2 = “10” 4. MISR Mode - 1 2 = “11” BILBO Modes (cont.)
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7 13 Scan-In X 0 1 0 D Q B 1 B 2 Y 0 Y 2 Y 1 D Q D Q SCK X 1 Scan-Out/X 2 Example of a 3-stage BILBO using a slightly different structure A NOR gate is added to each input path of D-FF
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Lecture 09 - BIST 03 - Testing and Testable Design...

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