hw03 - problem - 1 Consider the C17 benchmark(provided in...

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The University of Texas at Dallas Dept. of Electrical Engineering EE 6303: Digital Systems Testing HW # 3: Due on Thursday Oct. 2, 2008 When you submit your homeworks, to help us grade and identify your work, you need to comply with the following guidelines carefully: Have a cover page for your homework and write clearly: (1) your name as it appears in your student ID card , (2) course name/number, and (3) homework number. Identify the problems clearly by starting the solution of each problem on top of a new page and putting the problem number as given in the homework description. For example, for the problem 1 in this homework, you can put: HW#3 – Problem 1 on top of the page. Please staple the solution pages in order as given in the homework description. If you don’t have a solution for a problem, put a blank page with the problem number on top.
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Unformatted text preview: 1. Consider the C17 benchmark (provided in the course website). Perform fault collapsing for C17. Then, for test vector IN 1 IN 2 IN 3 IN 4 IN 5 01111: (a) Demonstrate parallel fault simulation. (b) Demonstrate deductive fault simulation. (c) Demonstrate concurrent fault simulation. (d) Demonstrate critical path tracing fault simulation. 2. Use Synopsys toolset to implement C17 at the gate level and find all faults detectable by the above single test vector. 3. One may argue that like many other statistical methods, fault sampling may be used to reduce the effort of fault simulation. Briefly, only a subset of randomly chosen faults (instead of the entire set) will be simulated. In at most one page, express your opinion on such technique in terms of application, accuracy and implementation. 1...
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