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Unformatted text preview: 1. Consider the C17 benchmark (provided in the course website). Perform fault collapsing for C17. Then, for test vector IN 1 IN 2 IN 3 IN 4 IN 5 01111: (a) Demonstrate parallel fault simulation. (b) Demonstrate deductive fault simulation. (c) Demonstrate concurrent fault simulation. (d) Demonstrate critical path tracing fault simulation. 2. Use Synopsys toolset to implement C17 at the gate level and find all faults detectable by the above single test vector. 3. One may argue that like many other statistical methods, fault sampling may be used to reduce the effort of fault simulation. Briefly, only a subset of randomly chosen faults (instead of the entire set) will be simulated. In at most one page, express your opinion on such technique in terms of application, accuracy and implementation. 1...
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- Fall '08
- Electrical Engineering