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Unformatted text preview: 1. Consider this circuit: Y Z k f h g e d A B C (a) Apply 6valued Dalgorithm to perform ATPG for SA1 fault on fanout branch h. (b) Apply PODEM algorithm and SCOAP measures to perform ATPG for SA1 fault on fanout branch h. 2. Consider the A SA0 fault in the circuit shown below: Flip Flop B A SA0 (a) Apply 5valued logic to find a test pattern. (b) Apply 9valued logic to find a test pattern. 1 3. Consider the aAZ path shown in this circuit: z B A C D b a x S1 U0 S1 S1 y (a) Find a nonrobust test for falling on the aAz path. (b) Suppose b S 1, a U 0, x S 1 and y S 1 is a test vector. If the permitted circuit delay is 3.5 units and gate A has a delay of 5 units and others have one time unit delay, sketch the relevant waveform to show that the test is not robust. (c) Can you derive a robust test? 2...
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 Fall '08
 MehrdadNourani
 Electrical Engineering, #, Logic gate, The Circuit, fanout branch h., Dallas Dept. of Electrical Engineering

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