hw04 - problem - 1. Consider this circuit: Y Z k f h g e d...

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The University of Texas at Dallas Dept. of Electrical Engineering EE 6303: Digital Systems Testing HW # 4: Due on Thursday Oct. 9, 2008 When you submit your homeworks, to help us grade and identify your work, you need to comply with the following guidelines carefully: Have a cover page for your homework and write clearly: (1) your name as it appears in your student ID card , (2) course name/number, and (3) homework number. Identify the problems clearly by starting the solution of each problem on top of a new page and putting the problem number as given in the homework description. For example, for the problem 1 in this homework, you can put: HW#4 – Problem 1 on top of the page. Please staple the solution pages in order as given in the homework description. If you don’t have a solution for a problem, put a blank page with the problem number on top.
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Unformatted text preview: 1. Consider this circuit: Y Z k f h g e d A B C (a) Apply 6-valued D-algorithm to perform ATPG for SA1 fault on fanout branch h. (b) Apply PODEM algorithm and SCOAP measures to perform ATPG for SA1 fault on fanout branch h. 2. Consider the A SA0 fault in the circuit shown below: Flip Flop B A SA0 (a) Apply 5-valued logic to find a test pattern. (b) Apply 9-valued logic to find a test pattern. 1 3. Consider the a-A-Z path shown in this circuit: z B A C D b a x S1 U0 S1 S1 y (a) Find a non-robust test for falling on the a-A-z path. (b) Suppose b S 1, a U 0, x S 1 and y S 1 is a test vector. If the permitted circuit delay is 3.5 units and gate A has a delay of 5 units and others have one time unit delay, sketch the relevant waveform to show that the test is not robust. (c) Can you derive a robust test? 2...
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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hw04 - problem - 1. Consider this circuit: Y Z k f h g e d...

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