hw05 - problem - options (rising vs. falling and robust vs....

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The University of Texas at Dallas Dept. of Electrical Engineering EE 6303: Digital Systems Testing HW # 5: Due on Thursday Oct. 30, 2008 When you submit your homeworks, to help us grade and identify your work, you need to comply with the following guidelines carefully: Have a cover page for your homework and write clearly: (1) your name as it appears in your student ID card , (2) course name/number, and (3) homework number. Identify the problems clearly by starting the solution of each problem on top of a new page and putting the problem number as given in the homework description. For example, for the problem 1 in this homework, you can put: HW#5 – Problem 1 on top of the page. Please staple the solution pages in order as given in the homework description. If you don’t have a solution for a problem, put a blank page with the problem number on top. 1. The ATPG in Tetramax has some options for path delay fault testing. For the circuit shown below try all
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Unformatted text preview: options (rising vs. falling and robust vs. non-robust) for all paths. Summarize the results in a table and provide a discussion. Outline the options and running steps in Tetramax that you used. x1 x2 x3 x5 z x4 c4 c3 c2 c1 2. What happens if there is a transition fault on the CS line of a DRAM? 3. Prove that MARCH C– test detects state coupling faults. M 0 : w ; M 1 : r w 1 ; M 2 : r 1 w ; M 3 : r w 1 ; M 4 : r 1 w ; M 5 : r 4. Prove that the MARCH C– test detects all inversion coupling faults ; . 5. Prove that the IFA-13 march test detects all stuck-open faults in the memory. M 0 : w ; M 1 : r w 1 r 1 ; M 2 : r 1 w r ; M 3 : r w 1 r 1 ; M 4 : r 1 w r ; Delay ; M 5 : r w 1 ; Delay ; M 6 : r 1 What is the testing time complexity of this march test in terms of n (the number of bits in the memory)? 1...
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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