Synopsys Tutorial - The University of Texas at Dallas Dept....

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1 The University of Texas at Dallas Dept. of Electrical Engineering EE 6301: Advanced Digital Logic EE 6303: Testing and Testable Design Instructor: Mehrdad Nourani A Quick Tool Setup and Tutorial for Simulation & Synthesis Using SYNOPSYS Toolset DISCLAIMER: The following steps aim at your setting SYNOPSYS toolset and running a sample VHDL program. SYNOPSYS is a large commercial CAD tool suite with many additional options that are not explained here. What we explain here is the minimum to run few tools. With this new version of SYNOPSYS that we installed, there might be problems in this document and some commands may not work exactly as explained. Proceed cautiously and use it at your own risk. We encourage you to assign enough time to familiarize yourself with this tool to be able to use it efficiently. Please report problems, corrections and suggestions about this document to nourani@utdallas.edu 1. Setting up SYNOPSYS in your account Most of the CAD tools, including SYNOPSYS, are accessible in various labs with UNIX workstations in EC building including EC 4.308 (VLSI CAD Lab) and EC 4.324 (Solarium Lab). More specifically, using workstations in EC 4.308 is recommended due to their faster speed and larger RAM. All CAD tools required for this course, run in VLSI CAD Lab. Due to frequent upgrades, sometimes they may not run in other labs. Many of these tools, including SYNOPSYS, provide shell commands to allow user run them without graphic user interface. This means that you can telnet to one of these machines remotely and run them without GUI. _ You need to be familiar with the basic UNIX commands and one UNIX text editor (VI, EMACS, GVIM, EDIT, etc.) . The “Quick UNIX Guide” also posted in the course website can be a good start. In order to run CAD tools in your UTD UNIX account, make sure that your environment variables are set correctly. Remember that in UNIX the files whose names start with a “.” (e.g. .login ) are hidden, to view them type “ls -a”. For bash users add the following line at the end of your .bash_profile file (watch carefully that there is a space between the period and the left-most slash). . /home/cad/startup/cadprofile_feb06 You need to logout and login again, or do one of the following: source .login source .bash_profile Alternatively, you can simply type source /home/cad/startup/cadprofile_feb06 at the prompt. Please note that if you source differently (i.e. the way that you source CAD files for other courses), you will need to close the console and open a new one to source as explained above. This would allow the environment variables to be taken into effect correctly. Having done these, you are ready for playing with VHDL and Scirocco.
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2 2. Steps for compilation with Scirocco Main steps in the SYNOPSYS VHDL System Simulator (VSS) environment are: 1. VHDL Code Development: You can use any text editor for this step.
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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Synopsys Tutorial - The University of Texas at Dallas Dept....

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