VHDLsimQR - VHDL Simulation Quick Reference Version...

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Unformatted text preview: VHDL Simulation Quick Reference Version 2002.06, June 2002 Comments? E-mail your comments about Synopsys documentation to doc@synopsys.com Copyright Notice and Proprietary Information Copyright 2002 Synopsys, Inc. All rights reserved. This software and documentation are owned by Snopsys, Inc., and furnished under a license agreement. The software and documentation may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: "This document is duplicated with the permission of Synopsys, Inc. for the exclusive use of _______________________________________ and its employees. This is copy number ___________." Destination Control Statement All technical data contained in this publication is subject to the export laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. Design Compiler, DesignTime, and PrimeTime are trademarks of Synopsys, Inc. All other trademarks are the exclusive property of their respective holders and should be treated as such. Printed in the U.S.A. Document Order Number 36545-000 MB VHDL Simulation Quick Reference, v2002.06 3Conventions Brackets [ ] indicate optional arguments. Italics indicate user-specified values. | indicates a choice among alternatives. Setting up the UNIX Environment This section describes how to set up the UNIX environment and how to view and print man pages from your UNIX environment. C-Shell Users Add the following lines to the end of your .cshrc file: setenv SYNOPSYS_SIM /usr/synopsys if (-e ${SYNOPSYS_SIM}/admin/setup/environ.csh) then source ${SYNOPSYS_SIM}/admin/setup/environ.csh endif If the software is installed in a directory other than /usr/synopsys, use that installation directory name instead. Bourne-shell and Korn-shell Users Add the following lines to the end of the .profile file: SYNOPSYS_SIM=/usr/synopsys export SYNOPSYS_SIM . ${SYNOPSYS_SIM}/admin/setup/environ.sh 3Conventions 3 If the software is installed in a directory other than /usr/synopsys, use that installation directory name instead. Viewing and Printing Man Pages You can view and print man pages for the invocation commands. From the UNIX prompt, use the following commands: % man command_name % man command_name | lpr -Pdevice Viewing Scirocco Control Language Commands You can view online help files for the Scirocco Control Language commands. From the simulator prompt, use the following command: # help -verbose command_name or use # command_name -help 4 Viewing Scirocco Control Language Commands Simulation Invocation Commands show_setup Displays settings from the synopsys_sim.setup files. vhdlan Invokes the VHDL Analyzer which analyzes VHDL source files and produces object files for both event and cycle simulation. vhdlan [options] filename_list Options are as follows: -nc Suppresses the Synopsys copyright message. -version Prints the analyzer's version number and exists. -licwait timeout Enables license queueing where timeout is the time in hours to wait for a license before finally exiting. -event Generates compiled and debuggable code for event simulation. -noevent Disables compiled code generation for event simulation. Debuggable event code is still created. The -event option takes precedence over the -noevent option. -cycle Generates cycle code for mixed event and cycle simulation and debuggable code for event simulation. -nocycle Disables cycle code generation. The -cycle option takes precedence over the -nocycle option. -vlib [vlibs] Specifies the order in which the Verilog libraries are to be searched for mixedhdl simulation. -work library Maps a design library name to the logical library name WORK. Simulation Invocation Commands 5 -cm line Enables line coverage for the VHDL file. -vhdl87 Lets you analyze non-portable VHDL code that contains object names that are now VHDL-93 reserved words. -output outfile Redirects standard output from VHDL Analyzer (that usually goes to the screen) to the file you specify as outfile. -list Creates a list file (.lis) containing the VHDL source code of the analyzed files, the names of the analyzed design units, and warning or error messages produced during analysis. -spc Performs VHDL Compiler synthesis policy checking. -bpc Performs Behavioral Compiler synthesis policy checking. -optimize This option is a modifier for the -event option. It speeds up compile mode simulation by eliminating certain VHDL checks. -no_opt Enables all VHDL language checks by cancelling the effect of -optimize. Use this option while debugging the VHDL source files in your design. -no_opt takes precedence over -optimize. -ccpath path Specifies the C compiler that the Analyzer must use for compiling the code from VHDL to C. -ccflags flags Specifies flags that vhdlan passes to the C compiler. -num_compilers vlaue Specifies the number of compilers the VHDL Analyzer uses to perform the parallel compilation. -parallel_compile_off VHDL Analyzer turns off parallel compilation of files and uses normal compilation. 6 Simulation Invocation Commands -xlrm Enables VHDL features beyond those described in LRM. -f file Specifies a file that expands vhdlan command line options. -noclkopt Disables certain clock optimizations. -nosbdopt Disables certain code optimizations. -ifcaseopt Enables beta if-case optimizations. -help Prints usage information for vhdlan. The default values for each vhdlan option are shown in brackets. VHDL_filename_list Specifies the VHDL source files to be analyzed. simcompiled Provides analysis information for a VHDL design unit. simcompiled [options] [libname.]design_unit [-u design_unit] Options are as follows: -nc Suppresses the Synopsys copyright message. -v Prints the program version number and exits without simulating. -o makefile Redirects standard output to the specified makefile. -only Prints the analyzer options used for only the design units you specify on the command line. -s libname Withholds printing of the analyzer options for the design library libname. By default, the analyzer options for the SYNOPSYS and IEEE libraries are not printed. Simulation Invocation Commands 7 [libname.]design_unit Specifies the design_unit you want to know the analyzer options for, with an optional logical library name. By default, the WORK library is assumed. The design_unit can be one of the following: cfgname Name of the configuration to get analyzer options for. You must use a configuration name to also retrieve analyzer options for any intermediate files on which the design unit depends. package Name of the package to get analyzer options for. entname [archname] Name of the entity and architecture to get analyzer options for. By default, archname is the most recently analyzed architecture. -u design_unit Specifies additional design units to get analyzer options for. You can use the -u option multiple times to specify different design units. simdepends Creates a list of target dependencies for simulation. This dependency file is then fed into the UNIX make utility to automatically update the necessary files. simdepends [options] [libname.]design_unit [-u design_unit] Options are as follows: -nc Suppresses the Synopsys copyright message. -v Prints the program version number and exits without simulating. -o makefile Redirects standard output to the specified makefile. -all Creates make targets for all required intermediate files. If simdepends cannot find a source file, it prints the target file with a directory specification of ... (for example, .../x.vhd). By default, simdepends only prints the targets for the intermediate files for which it finds a source file. 8 Simulation Invocation Commands -only Prints make targets for only the design units specified on the command line but not for the intermediate files on which they depend. -s libname Withholds printing of dependencies and targets from the specified library. By default, this option is assumed for the SYNOPSYS and IEEE libraries unless you specify the -all option. [libname.]design_unit Specifies the design_unit to build make targets for, with an optional logical library name. By default, the WORK library is assumed. The design_unit can be one of the following: cfgname Name of the configuration to create a make target for. You must use a configuration name to also build make targets for any intermediate files on which the design unit depends. package Name of the package to create a make target for. entname [archname] Name of the entity and architecture to create make targets for. By default, archname is the most recently analyzed architecture. -u design_unit Specifies additional design units to create make targets for. You can use the -u option multiple times to specify different design units. scs Invokes the Scirocco Compiler which elaborates and compiles the design, and generates simulation executable for running the simulation. scs [options] [libname.]design_unit Options are as follows: -nc Suppresses the Synopsys copyright message. -version Prints the program version number and exits without running the program. Simulation Invocation Commands 9 -verbose Prints the verbose error messages about the status of the simulation. For use with the VhPLI interface. -licwait timeout Enables license queueing where timeout is the time in hours to wait for a license before finally exiting. -output outfile Redirects all standard output to the file outfile. -executable sim_exec Renames the simulation executable to the name specified by sim_exec. Default name is scsim. -file scs_file Reads scs_file for program arguments. -nodb Turns off creation of database directory. -partition partfile Specifies to use the file partfile for retrieving cycle and event partition elaboration information. Use this option to run in mixed event and cycle mode simulation. For information about how to create a partition file, see "Partition File" on page 19. -2state Creates 2-state (0,1) code for cycle design partitions. Default code generation is 4-state. Using -4state option in the partition file overrides this setting for the partition. -noperf Creates less optimized version of the code for cycle design partitions. Used for better cycle debugging. Default code generation is perf (optimized). Using -perf option in the partition file overrides this setting for the partition. -monsigs filename Specifies a file that contains a list of absolute pathnames of VHDL signals and variables. You can specify these signals and variables as either readable or writable. When running the cycle portion of your design in perf mode, the value of a signal or variable might not be visible. To make the specified signals and variables visible, you can use the monsigs file to stop the simulator from optimizing the objects. 10 Simulation Invocation Commands A signal or variable must be readable to allow tracing or viewing the value from the simulator prompt. Simulating the cycle portion of your design in debug mode is equivalent to specifying every signal and variable in the cycle block in a monsigs file. You can use the assign and hold commands only with signals or variables that are writable. You can use the monsigs option multiple times for each partition to specify different monsigs files. This option slows down the simulation speed. -cm_dir name Specifies where coverage database to be stored. -cm_name filename Specifies the name of generated coverage and report files. -cm_log filename Specifies the name of covermeter log file name. -perf_data data_file Displays detailed information on all the triggers and combinational logic blocks in the design unit along with the elaboration statistics. -time base_time Sets the simulation base time units to base_time. The default simulation base time is NS. -generics cmdfile Enables you to assign top-level generics from the file cmdfile. -ccpath path Specifies the C compiler that scs must use for compiling the design. -ccflags flags Specifies flags that scs passes to the C compiler. -verilogcomp "vcs_options" Specifies the VCS compilation options to be used when compiling mixed language design. -mhdl Specifies mixed language mode. -maxLayers value Sets the max number of donut layers for mixedhdl design. Simulation Invocation Commands 11 -help Prints usage information for common scs options. [libname.]design_unit Specifies the design_unit you want to simulate, with an optional logical library name. By default, the library mapped to the WORK variable is used. The design_unit can be one of the following: cfgname Name of the configuration to be simulated. entname [archname] Name of the entity and architecture to be simulated. By default, archname is the most recently analyzed architecture. scsim Executable generated by scs. Launches a simulation session from the command line. scsim [options] Options are as follows: -nc Suppresses the Synopsys copyright message. -version Prints the program version number and exits without simulating. -signature Prints the scs compile-time options uesd to create scsim. -verbose Prints the verbose error messages about the status of the simulation. For use with the VhPLI interface. -licwait timeout Enables license queueing where timeout is the time in hours to wait for a license before finally exiting. -output outfile Redirects all standard output to the file outfile. -include cmdfile Reads, executes, and echoes commands in the file cmdfile. 12 Simulation Invocation Commands -log [logfile] Records simulator commands from the command-line or the GUI to a logfile. By default, all commands are logged in the file scirocco_command.log. -cm line Enables line coverage during simulation. -cm_dir name Specifies where coverage database to be stored. -cm_name filename Specifies the name of generated coverage and report files. -cm_log filename Specifies the name of covermeter log file name. -debug_all Performs debug event simulation on the entire design. The debug_all option overrides the -partition option. Using this option gives the poorest simulation performance. Use it for source line debugging only. -debug_unit design_unit Performs debug event simulation on the specified design unit. Use it for source line debugging only on a single block or design unit while the rest of the design can still run in compiled event or cycle mode. -profile profile.htm Generates a dynamic simulation performance profile report in the profile.htm file. This file is in HTML format and is viewable with any HTML file browser. -vhpi library_name:entry_point_function:model_name Loads foreign VHPI applications into the Scirocco simulator. library_name is the platform independent name of the foreign application to be loaded. entry_point_function is the name of the C function that is the entry point to the application. model_name is a unique proper name associated with the application. -verilogrun "vcs_options" Specifies the VCS runtime options to be used when simulation a mixed language design. -file scsim_file Reads scsim_file for program arguments. Simulation Invocation Commands 13 -novitaltiming Enables functional-only simulation of VITAL components. All timing information is discarded for VITAL models during simulation. -vpddeltacapture Enables VPD delta cycle capture when tracing objects in your design to be viewed in the GUI waveform window. -xlrm Enables VHDL features beyond those described in LRM. -nopgroupopt Disables certain runtime optimizations. -noactivecheck Disables checking for optimized frivers for signals with transaction-based attributes. -restore Restores simulation state from a checkpoint file. -sdf [min:|typ:|max:][region:]sdf_file Backannotates the portion of the design below region, using timing values from sdf_file. Use one of the following options: min Backannotates the design with minimum timing values. typ Backannotates the design using typical timing values. max Backannotates the design with maximum timing values. If you do not specify timing option, Scirocco uses the typical timing values. -sdf_af Creates an assign file that contains generics and their values from sdf_file. The assign file is called sdf_file.inc. This file is useful only for debugging the SDF file. -help Prints usage information for common scsim options. 14 Simulation Invocation Commands scirocco Launches VirSim GUI for interactive simulation session with Scirocco. scirocco [options] Options are all valid scsim options. cmView Writes reports about coverage and displays coverage metrics. cmView [options] Options are as follows: -b Invokes cmView in batch mode. In batch mode cmView writes reports instead of starting the GUI. -cm line Specifies reading the design file and the intermediate data files for the specified line coverage type. -cm_autograde percentage Tells cmView to do test autograding in batch mode and write a test autograding report. -cm_dir directory_path_name Specifies an alternative name and location for the scsim.cm directory. -cm_hier filename Specifies a file containing a list of module instances. cmView displays or reports coverage for only these instances and their subhierarchies. -cm_log filename Specifies a log file. -cm_map Maps the coverage for a subhierarchy from one design to another. -cm_name filename Specifies the name of the report files. -cm_report annotate Tells cmView to write annotated files in the scsim.cm/reports/annotated directory. Annotated files show you where you are missing line coverage. Simulation Invocation Commands 15 +cm+lic+wait You need a license to run cmView. If a license is not available at the moment, you can tell cmView to wait for a license instead of automatically terminating with the +cm+lic+wait command line option. -help Displays a help message. vpd2vcd Converts VPD output to VCD output. vpd2vcd [options] vpd_file [vcd_file] Options are as follows -h Translates hierarchy information only. -q Suppresses printing of copyright and other informational messages. -s Allows sign extension for vectors. Reduces size of vcd_file. -x Expands vector variables to full length when displaying $dumpoff value blocks. +ignoredelta Ignores delta cycle values if they exist in the VPD file. +morevhdl Translates the VHDL types that are not directly mappable to Verilog types in addition to the ones that are mappable. vcdiff Compares two VCD files. vcdiff vcd_file_1 vcd_file_2 [options] Options are as follows -onlysigmiss Reports only those signal misses whose corresponding scope exists. -absentsigscope scope Signals absent in the given scope will be reported. 16 Simulation Invocation Commands -allabsentsig Outputs all signals absent in either vcd (by default, outputs upto 10 signals from both vcd to standard output). -absentfile file Outputs signals absent in either vcd to the given file rather than standard output. -min N Minimum time to be scanned. -max N Maximum time to be scanned. -scope scope Reports only for scope and offspring. -level N Report only N levels from top or scope. -include file Reports only for signals and scopes listed in the file. -ignore file Ignores signals and scopes listed in the file. -ignoreRegs Ignores diffs in REG vars. -ignoreWires Ignores diffs in WIRE vars. -ignoreReals Ignores diffs in REAL vars. -ignoreTiming time Ignores timing diffs less than time. -strobe N M Compares signals after N time units then after every M time units. -prestrobe Directs -strobe to compare just before strobe times. -synch signal Shows diffs when signal changes. -synch0 signal Shows diffs when signal changes to 0. -synch1 signal Shows diffs when signal changes to 1. Simulation Invocation Commands 17 -xzmatch Always treats x and z values as non-diffs (by default, they are non-diffs at time 0). -noxzmatchat0 Suppresses treating x and z values as non-diffs at time 0. -wrapsize N Vector size to wrap value display (def:64). -contextDiff N Displays diffs in context. -dots N Displays a period to stderr every N or so lines. -showmasters Shows vxl collapsed net masters. -allsigdiffs Shows all diffs on signal, not just first. -limitdiffs Number of differences after which to exit (default 50, 0 for no limit). -matchSignals Reports signal mismatches as errors. -geninclude filename Generates a vcat include file from diffs. -spikes Annotate signals with spikes when diffs found. -errfile filename File to write mismatched signal errors. -configGen src_config_file Generate virsim config file so that virsim can be used to view diffs. src_config_file defaults to default.cfg. -mt Runs in mutil-threaded mode. 18 Simulation Invocation Commands Partition File The partition file contains partition information about the design for all design units to run in cycle mode.To perform mixed cycle and event mode simulation in Scirocco, you must create a partition file for use with the scs -partition command. For each top-level design unit that is to run in cycle mode, you must specify a partition statement in the partition file, otherwise the design unit runs in event mode. To add a comment to the partition file, begin the line with the # character. Line continuation is not allowed. The syntax for the partition statement is as follows: cycle [options] [libname.]design_unit Options are as follows: -2state Creates 2-state (0, 1) executable code. 2-state code allows Z values for bus signals. 2-state code is faster than 4-state code. The -2state option and the -4state option are mutually exclusive. -2state is the default. -4state Creates 4-state (0, 1, X, Z) code. The -4state option and the -2state options are mutually exclusive. -perf Creates a version of executable code that is a fully optimized and less observable (limited debugging). Code generated using -perf is faster than code generated with -debug. The -perf and -debug options are mutually exclusive. -perf is the default. -noperf Creates a version of executable code that is fully observable and less optimized. The -debug option and the -perf option are mutually exclusive. -latch_transparency All latch based processes will use their sensitivity list as the trigger instead of the enable. This is a dangerous switch and is only to be used in a flip-flop based design containing few latches. Partition File 19 -latch_style style Specifies the type of edge to be used as the trigger edge where style is leading, trailing, or event. trailing is the default. -tbl Enables Scirocco table optimization in the cycle portions of the design. [libname.]design_unit Specifies the top-level configuration or entity of the design (sub)tree to be elaborated. An optional logical library name may also be specified. By default, the library mapped to the WORK variable is used. If you specify an entity, a default configuration will be created and used for simulation. The simulator always uses the most recently analyzed architecture. If you specify your own top-level cycle configuration, you must have a corresponding "use configuration" clause explicitly stated in the configuration of the event block where the cycle subtree is being instantiated. 20 Partition File Scirocco Simulation Control Language The Scirocco Control Language is Tcl, augmented by Scirocco-specific commands and variables. Listed here are the Scirocco-specific commands. alias name definition Creates a pseudonym or shorthand for a command or series of commands. apropos [-symbols_only] [pattern] Searches the command database for a pattern match. If you specify -symbols_only, the command only searchs the list of command names and options. assign [-after delay_value] vhdl_expression {name_list} Assigns values to specified variables and signals. Variables and signals in cycle subtrees must be listed using the -monsigs option of the partition statement. breakpoint A breakpoint in Scirocco can be created using the monitor -s command. See the monitor command for more information. call procedure_name Executes the specified VHDL procedure. Event mode only. cd [region] Sets the working region to region. If no region is specified, the root (/) becomes the region. checkpoint filename Saves the current state of the simulation, into filename, so it can be restored later. Scirocco Simulation Control Language 21 Control-c Interrupts the simulation. create_command_group group_name Creates a command group to be displayed when you use the help command. You can add custom Tcl procedures in this group. define_proc_attributes [-info "info_text"] [-define_args {{arg_val "info_text" disp_arg_val}{...}}] [-command_group group_name] [-permanent] [-hide_body] [-dont_abbrev] name Defines various attributes to be added to a Tcl procedure. -info "info_text" Defines a help string for the procedure. -define_args Defines the procedure arguments, specified by arg_val, to be listed for verbose help. disp_arg_val is the name assigned to the argument when displayed on the screen. -command_group group_name Defines the command group to list the procedure in. -permanent Prevents the procedure from future overwrittings. -hide_body Does not allow the procedure body to be viewed with `info body'. -dont_abbrev Does not allow the procedure to be abbreviated. drivers [-d | -e] signal_name_list Displays a list of signals that drive the indicated signals. Event mode only. -d Driving value for each driver. -e Effective value for each driver. 22 Scirocco Simulation Control Language dump [-help] [-delete [-vpd|-vcd|-evcd] "trace_list"] {[-vpd]|-vcd|-evcd}[-o filename] [-list "trace_list"] [-compiled monsigs_filename] [-no_verilog] [-no_vhdl] [-line filename "[start_line [, end_line]]"] [-strobe "interval[,start_time [, stop_time]]"] [-all|-deep [-depth "depth"]] {region(s)/object(s)/filename} Creates one or more traces. -delete [-vpd|-vcd|-evcd] "trace_list" Deletes the traces with the specified formats. -vpd | -vcd | -evcd Specifies the output file format to be VCD+, VCD, or eVCD. VCD+ (-vpd) is the default format. -list "trace_list" Returns a list of the selected traces and what they trace. -compiled monsigs_filename Generates a monsigs file for the next simulation session. -no_verilog Use this option only in mixed language designs. Specifies that a Verilog dump is not needed. -no_vhdl Use this option only in mixed language designs. Specifies that a VHDL dump is not needed. -all Provides a faster method for creating a trace for every signal and port in the design at and below the specified region. -deep region_name Creates a trace for every signal and port in the design at and below the specified region. -depth "depth" Specifies the number of levels down the hierarchy to traverse. -line "source_file start_line[,end_line]" Traces the specified lines of source code in the file source_file, from start_line to end_line in VPD format only. Scirocco Simulation Control Language 23 -strobe "interval [,start_time [, stop_time]]" objects Creates traces from start_time to stop_time at every interval time in VPD format only. -o file_name Lets you specify the output filename when you create the first dump of a particular format. region(s)/object(s)/filename Details on the operation of the trace. The syntax of this option depends on what you want to trace. dump_memory [-ascii_h | -ascii_o | -ascii_b] memoryName [dataFileName] Stores the contents of a RAM or ROM instance to a file, dataFileName. If dataFileName is not specified, the memory contents are displayed to STDOUT. The memory can be a simple VHDL variable or a sparse memory. -ascii_h | -ascii_o | -ascii_b Sets the base value for displaying the memory contents to hexadecimal, octal, or binary respectively. The default value is hexadecimal. echo -n ["text_string"] [$variable_name] Displays simulator variable values and text strings. environment Displays information about the current simulation environment. error_info Displays more detailed information about errors from Tcl procedures and commands. evaluate vhdl_expression_list Prints the value of the specified VHDL expressions. Enclose expressions with spaces or wildcards in parentheses. Replace slashes (for division) with double slashes. 24 Scirocco Simulation Control Language fprint format_string arg_list Prints formatted output. format_string must be a VHDL expression of type STRING. Each character in format_string is copied literally (from left to right) to the output, except for conversion specifications and backslash-escapes. Arguments are matched with conversion specifications in serial order. The value of each argument is converted to a string according to the corresponding specification, that string is inserted into the output stream in place of the specification. Each conversion specification begins with a percent sign (%) and ends with a conversion character. Following is a list and description of the conversion characters: b, o, x Bit-vectors printed in binary, octal, or hex format. r "Reasonable" default format. t Text literal (the argument is not evaluated as a VHDL expression). c Character literal. s String. e, f, g Floating-point (as in the C language printf statement). The t, s, d, e, f, and g conversion specifications can also include a width and precision specification between the % and the conversion character (as in the C language printf statement). Scirocco Simulation Control Language 25 You can insert special characters into the output stream by including the corresponding backslash escapes in the format string. The backslash escapes are \n for new-line, \t for tab, \\ for backslash, and \ddd for the bit pattern corresponding to the (one, two, or three) octal digits ddd. help [-verbose] [pattern] Prints information about specified subjects. If no arguments are specified, help displays the full list of available commands. history [-h] [-r] [keep number] [nextid] [redo [event]] [substitute old new [event]] Tracks recent commands. With no options, history displays the history list. -h Displays the history without leading numbers. -r Displays the history in reverse order. keep number Determines how many commands are kept in the history list. nextid Returns the serial number that is assigned to the next recorded command. redo [event] Re-executes a specified command. If event is positive, the command with that serial number is re-executed. If event is negative, the command event up from the bottom of the queue is re-executed. If event is a string, the most recent command whose first letters match the string is re-executed. The default value of event is -1 (executes the previous command.) Shortcuts !event is a shortcut form of history redo event. !! is a shortcut form of history redo -1. 26 Scirocco Simulation Control Language history substitute old new [event] retrieves the specified old command and substitutes it with the new command. You specify an event as in history redo. ^old^new is a shortcut form of history substitute old new. hold [-after delay] (vhdl_expression) signal_name_list Holds the value of the selected signals to the value of the specified VHDL expression. The hold ends when you assign a new value to the signal with the assign command. Debuggable event mode only. info Prints information about the internal state of the Tcl interpreter. Some of the important options are as follow: info args procName Returns a list of arguments in the order that the procedure procName expects. info body procName Returns the body of procedure procName. info cmdcount Returns the number of commands executed in the current session. info commands [pattern] Returns a list of command names available. If pattern is specified, only the commands that match the pattern are returned. info exists varName Returns one if the variable varName exists, otherwise, it returns zero. info procs [pattern] Returns a list of all the procedure names in the current environment. If pattern is specified, only the names that match the pattern are returned. info script Returns the name of the currently executing script file if there is one, otherwise, it returns an empty string. Scirocco Simulation Control Language 27 info vars [pattern] Returns a list of all the variable names in the current environment. If pattern is specified, only the names that match the pattern are returned. is_false value Returns a 1 if value is `False' or `0'. is_true value Returns a 1 if value is `True' or `1'. lminus list "elements" Returns the selected list without the specified elements. load_memory memoryName dataFileName Loads a VHDL memory with the information from a data file. The memory can be a simple VHDL variable or a sparse memory. ls [-t] [-v] [-m] {object_name} Lists VHDL objects. -t Prints the types of objects. -v Prints the values of the objects. -m Prints the mode the objects are simulated in (event or cycle). monitor Options for creating a new monitor are [-c | -s] [-n monitor_name] [-cmd "exec_cmd"] [-expr (cond_expr)] [-o outfile] mon_spec where mon_spec is one of the following: 28 Scirocco Simulation Control Language [-at abs_time] [-after rel_time] [-strobe start_time,time_interval[,stop_time]] [-on "source_file start_line[, end_line]] [-off "source_file start_line[, end_line]] [-read "var_list"] [-write "var_list"] [-active "signal_list"] [-event "signal_list"] [-call "subprog_list"] [-elaborate "subprog_list"] [-return "subprog_list"] [-tprocess "process_list"] [-block "process_list"] [-unblock "process_list"] Options for modifying or removing existing monitors are [-rename "old_name new_name"] [-enable "mon_list"] [-disable "mon_list"] [-list "mon_list"] [-delete "mon_list"] [-stop "mon_list"] [-continue "mon_list"] The monitor command creates monitors or breakpoints in the VHDL source code. You cannot specify options for creating monitors together with options for modifying monitors. When creating a new monitor, the options in the first group must be specified before mon_spec. -c Creates continues monitors. -c is the default. -s Creates stop monitors. -name mon_name Names the monitor mon_name. -cmd "exec_cmd" Specifies the command, expression or procedure to be executed when the monitor fires. -expr "cond_expr" Defines a conditional expression that determines whether to trigger the monitor. This option can only be used in conjunction with -event, -read, and -write monitors. Scirocco Simulation Control Language 29 -o outfile Redirects the output to outfile instead of STDOUT. -at abs_time Creates a monitor that fires at abs_time. -after rel_time Creates a monitor that fires at regular intervals starting rel_time after the monitor is created. -on "filename start_line[,end_line]" Creates a monitor that fires when a specified set of source code lines are executed. Debug mode only. -off "filename start_line[,end_line]" Deactivates monitors and commands for specified lines of source code. Debug mode only. -read "var_list" Creates a monitor that fires when a variable is read. Debug mode only. -write "var_list" Creates a monitor that fires when a variable is written to. Debug mode only. -active "signal_list" Creates a monitor that triggers when a value is assigned to a signal, even if the signal value does not change. Event mode only. -event "signal_list" Triggers the monitor on any event on the list of signals. For signals in a cycle block, the signals must be specified using the -monsigs option in the partition file. -call "subprog_list" Creates a monitor that triggers when a subprogram is called. Debug mode only. -elaborate "subprog_list" Creates a monitor that triggers when a subprogram is elaborated. Debug mode only. -return "subprog_list" Creates a monitor that triggers when control is returned from a sub_program to the calling program.Debug mode only. -tprocess "process_list" Triggers a monitor when the specified process is executed. Debug mode only. 30 Scirocco Simulation Control Language -block "process_list" Creates a monitor that triggers each time a wait statement is executes in the specified process or subprogram. Event mode only. -unblock "process_list" Creates a monitor that triggers each time execution resumes after a wait statement in the specified process or subprogram. Event mode only. -rename "src dest" Renames an existing monitor. -enable "mon_list" Enables the selected monitors if they have been disabled. -disable "mon_list" Disables the selected monitors if they have been enabled. -list "mon_list" Returns a list of the selected monitors and their triggers. -delete "mon_list" Removes the specified monitors. -stop "mon_list" Changes a continue monitor to a stop monitor. -continue "mon_list" Changes a stop monitor to a continue monitor. next [n] Executes n number of lines of VHDL code (default is one line). The next command remains inside the current process, and does not step into subprograms, or count or stop on lines controlled by an off monitor. Debug mode only. parse_proc_arguments -args arg_list result_array Parses the procedure arguments into the specified array. This command only works from within a procedure. Scirocco Simulation Control Language 31 print_suppressed_messages Displays a list of the message IDs that are currently being suppressed.A message ID is the name of an error message that appears in parenthesis, for example (CMD-029). printenv [variable_name] Displays the values of shell environment variables. If a variable name is provided, only variables matching the specified variable name are displayed. printvar [-application] [-user_defined] [pattern] Displays the values of one or more variables. If a pattern is provided, only variables matching the pattern are displayed. -application Displays only application variables. -user_defined Displays only user_defined variables. proc_args proc_name Returns a list of argument names of the specified procedure in the same order they were specified. proc_body proc_name Returns the body of the specified procedure exactly as it was specified. pwd Displays the name of the current working region. quit Quits the simulation and exits to the operating system. 32 Scirocco Simulation Control Language redirect [-append] file_name "command_string" Redirects the output from the specified command_string into the specified file. This command supports nested level redirection. If you use -append, the output is appended to the end of the specified file. Use this command instead of redirection arrows (>, >>). restart Restarts the simulator to time zero. All commands not affecting values of the simulation will be re-executed. restore filename Restores, from filename, the state of a previously saved simulation so the simulation can be continued from where it was last saved. run [delta_time] Runs the simulation forward from the current time to maximum simulation time period as specified by delta_time. set variable_name [value | vhdl_expression] Assigns values to the specified simulator shell variables. With no arguments, set displays the current values of all simulator shell variables. set_unix_variable variable new_value Sets the value of a system environment variable. setenv variable new_value Sets the value of a system environment variable. sh command_list Executes the specified commands in a child process. Works much like the Unix sh command, allowing piping and file redirection. Scirocco Simulation Control Language 33 source [-echo] [-verbose] cmdfile Reads a file and executes it as a script. -echo Echos all commands. -verbose Displays intermediate results. status [-t] [process_name | signal_name] Displays the ready-to-run queue and a list of the processes that are waiting for events on signals. If you specify a process or signal name, the simulator displays information only about that signal or process. step [n] Executes n number of lines of VHDL source code (default is one line). Unlike next, step does step into subprograms. When executed, step does not count or stop on lines controlled by an off monitor. Debuggable event mode only. suppress_message "message_list" Supresses the printing of all specified messages. unalias name Removes a pseudonym or shorthand for a command. unset variable_name_list Resets predefined simulator variables to their default values and clears user-defined variables. unsuppress_message "message_list" Unsupresses the printing of all specified messages. where [process_name] Displays a stack back trace for the specified process. 34 Scirocco Simulation Control Language which "filename_list" Locates a file and displays its pathname. Only searches the path specified by the variable search_path. VirSim Quick Reference This section describes the VirSim GUI commands and windows within Scirocco. Starting VirSim GUI To start the VirSim GUI for interactive or VCD+ postprocessing analysis, type scirocco [options] [options] Options are all valid scsim options. Statement Execution Capture To capture statement execution data to a VCD+ file, use # dump -line "source_file start_line [, end_line] See also the syntax for the dump command in the previous section. VCD+ Post-Processing Analysis Specify command line options to simulator. Run simulator to generate VCD+ file. Specify command line options to VirSim to open VCD+ files, load a configuration, and so on. Open multiple instances and types of VirSim windows. VirSim Quick Reference 35 The following table shows the options for using VirSim in post simulation mode or interactive mode with Scirocco. For example, type scirocco +vpdfile+my_vpd_file VirSim Option Post Simulation or Interactive Mode Task +vpdfile+<VCD+ file to open> +vcdfile+<VCD file to open> +cfgfile+<cfg file to load> Opens a VCD+ file Opens a VCD file Loads a configuration Interactive Analysis Specify command line options to scirocco to load files and configurations and start simulator. Run simulator in VirSim Interactive Window. The following table shows the additional options for using GUI interactively with Scirocco. VirSim Option Interactive Mode Task +simtype+Scirocco Specifies the simulator. This argument is casesensitive, you must type Scirocco. Passes simulator command line options to GUI. +simargs+"<design_unit>" +cfgfile+<cfg_file_name> 36 VirSim Quick Reference Signal Selection The following tables describe how to use the left (LM), middle (MM), and right (RM) mouse buttons to select signals. On a two button mouse with Exceed, typically pressing LM with RM is the same as MM. To Drag and Drop using the PC version of VirSim, LM to select, LM again and drag. Signal Selection in Mouse Button Hierarchy Browser and Waveform Window Select one signal Select group of signals Click LM on the signal. Click LM on first signal, hold Shift and click LM on last signal in the group. Hold Ctrl and click LM on first signal, then hold Shift and click LM on last signal. Hold Ctrl and click LM on signals. Hold Ctrl and click LM on selected signals. Deselect group Add non-contiguous signal to a group of selected signals Deselect selected signals Signal/Item Selection in Mouse Button Register Window and Source Window Select one signal or item Select all items in an area Click LM on the item. Click LM on corner of an area, drag selection box over items in Register window. Hold Shift and click LM on last item in Register Window. Hold Ctrl and click LM on selected signals. Add non-contiguous item to a group of selected items Deselect selected signals VirSim Quick Reference 37 Move and Copy The following table describes how to move or copy scopes, signals, and text within or between windows. Move or Copy Mouse Button Move a signal within a window Move a signal between different windows Copy a signal within a window Copy a signal between different windows Click MM on the signal then drag and drop Hold Shift and click MM on the signal then drag and drop to another window Hold Ctrl and click MM and drag to copy Click MM on the signal then drag and drop Dialog Box Text Entry Delete text Ctrl u Backspace Ctrl b Save and Load Configuration To save the current session state, select File-> Save Configuration->, enter name or select a name, click LM, and click OK. To load a saved session state, select File-> Load Configuration->, enter name or select a name, click LM, and click OK. Linking Windows Interactive Window, Register Window, Waveform Window, and Source Window can be linked to follow in time. Use the SIM and Unlink menu options to link and unlink windows. 38 VirSim Quick Reference SIM links windows to interactive simulator. When linked to SIM, VirSim commands move the Browser forward in time advance the simulator, and VirSim commands that take the Browser back in simulation time are disabled. Unlink unlinks the window from any existing links. When a window is invoked from the Interactive Window, the new window will be linked to SIM. When a windows is invoked from the VirSim Main Menu, it will be unlinked. Link/Open/Unlink Mouse Button Link to previously opened window Open a new window and link to it Unlink LM on Link icon, LM on Link Select Window-> Select Window LM on Link icon, LM on Unlink Signal Groups Signal Groups are logical groupings of signals that are global to all windows. Signal Groups Mouse and Command Selection Create Click LM on Groups icon and select New Group. Enter new name and click LM on Add. AutoGroups are created when you drop of a scope/signal into the Signal Name Pane of the Waveform Window. Click LM on Group Icon and select Edit-> Groups, select Group, enter Group Name, LM on Rename Display Rename VirSim Quick Reference 39 Markers In Time Markers in time are bookmarks in time for the Waveform Window, Source Window, and Register Window. Marker Commands Create Edit-> Markers, enter name and {time or C1 in Waveform Window}, LM on Add Click LM on Marker Icon, click LM on Marker Name in popup menu Click Save Zoom toggle button to return to zoom factor when selecting marker View Save Zoom Factor Expressions You can create buses and define search conditions using VHDL expression syntax for Waveform Window and Register Window. You can also, view potential changes without editing source. Expressions Commands Create Edit-> Expressions, enter name, enter or drag and drop Trigger and/or Expression, LM on Add Drag and drop from Breakpoints pane to a window, LM on search arrows in window Make changes, LM on Update LM on name, LM on Delete LM on button by name in Breakpoints pane to enable/disable search controls View Change Delete Search Control 40 VirSim Quick Reference Interactive Window The Interactive Window provides graphical interactive simulator control. Task Simulator Commands Command Prompt LM on Command text entry box enter command, and click Return Sim->Invoke Sim, select sim type and type command line, and click OK Sim->Re-exec Pressing button sends command yellow fonts require an object to be selected. Step time, signal or go to time Displays current scope and time Enter run or LM on Arrow button LM on Stop Invoke simulator Re-start simulator User Defined Buttons Pane Step Time control Begin/Continue Sim Stop/interrupt Simulation Interactive Window 41 Hierarchy Browser Hierarchy Browser lets you View and traverse design hierarchy Drag and drop scopes or signals to other windows Filter scopes/signals to find those of interest List signals in Signal List Pane and focus selected scope in Hierarchy pane Add selected signals to an existing Signal Group Traversing Design Hierarchy The following table shows how you can navigate the hierarchy of your design. Traversing Mouse Selection Down Up View Signals LM on Down Arrow left of parent scope LM on Up Arrow left of child scope LM on scope in Hierarchy Pane, or MM on scope and Drag and Drop to Signal Select Pane RM in Hierarchy Pane, select Create Root LM on [Root Icon], select bookmark of interest RM in Hierarchy Pane, select Go To Top Create root Select root Jump to Top 42 Hierarchy Browser One-level vs. Multi-level View To change your display, click LM on Display then select One-Level or Multi-Level. Select View Display One Level Multi-Level One parent and its children Traversed scopes and children Search Pane Select Scopes or Signals button and scope(s) of interest in Hierarchy Pane. Select Hierarchy Range: All, Selected, or Children. Type text string in Search pane filter field. Use * and ? as wildcards, or * for no filter. LM on Search. Signal Select Pane Select the Constants, Generics, Variables, Signals, and/or Ports buttons. Type text string in Signal Select pane filter field.Use * and ? as wildcards and LM on Filter or * for no filter. LM on scope in Hierarchy pane or drag and drop scope to Signal Select Pane. Add Signal to A Group Select signals in Signal Select Pane. LM on group menu, select a group. LM on Add. Adjust Pane Layout LM on Display, select Default, Vertical or Horizontal. Hierarchy Browser 43 Select VCD+ file to View If multiple VCD+ files are open, select [Design Icon] and select desired file from popup menu. Select Top Level Module to View For designs with multiple top level modules, or roots, VirSim displays the first one alphabetically. To view a different root, LM on the [Root Icon] and select the desired root from the popup menu. Update the Hierarchy To update the Hierarchy after re-simulating the design, select File -> Update. Waveform Window Common debugging tasks in the Waveform Window are as follows: Edit-> Groups/ Markers/ Expressions/ Breakpoints Edit-> Styles to personalize Waveform Style. Drag and Drop scope/signals to view waveforms. View changes within a simulation time, that is, Delta Cycle. Use Accelerator Keys to scroll the waveform pane. Signal Name Pane Double click LM on vector name to Expand/Collapse displayed vectors. 44 Waveform Window Time Pane To enable the RM menu commands for the Delta Cycle tasks listed in the following table, you must first use the -vpddeltacapture option when invoking scsim. Task Mouse Button Set C1 cursor at time Set C2 cursor at time Zoom to cursors View Delta Cycle changes Collapse a Delta Cycle View Collapse all Delta Cycle Views LM MM RM RM (on transition) ->Expand Time RM->Collapse Time RM->Collapse All Time Waveform Pane Task Mouse Button Set C1 cursor at signal edge Set C2 cursor at signal edge Zoom to cursors Vertical Zoom on Waveforms Jump to Previous/Next edge of selected signal(s) Add a Blank line Move up/down one signal Move up/Down one Page Go To Top/Bottom LM MM Ctrl+RM Click Vertical Zoom Icon Highlight signal(s), place C1 cursor, type N or P. (The window must be unlinked) RM->Add Blank Up/Down Arrow Shift+Up/Down Arrow Ctrl+Up/Down Arrow Waveform Window 45 Signal Value Pane Text display of signal values at C1 cursor time. To Select a Predefined Radix, RM on value. Print and Save Waveforms Task Command Print Save/ Print to file File->Print, [select options], LM on OK File->Print, LM on Print Only to File [select desired options], LM on OK [saves in ps format or encapsulated ps] Register Window Common tasks in the Register Window are as follows: Control graphical display of signal data by creating text, lines, boxes, intermixed signal data. Drag and drop VHDL source from Source Window or signals into Register Window. View signal data at selected marker or breakpoint Use the Graphics utilities from the Graphics pull down menu. Use Pink Arrow buttons to view next or previous change. Jump to desired time by LM on Time text entry box, enter time>, and click OK. View unique event indicators with Display->Unique Events. This is default on. 46 Register Window Source Window Common debugging tasks in the Source Window are as follows: View VHDL source code. Set line breakpoints and replay statement execution. View statement execution at selected marker time. View signal values with pop-up labels. Dynamically view signal values as simulation running. Drag and drop source to Register Window or Waveform Window to view signals. Source Text Pane In the Source text pane, you can Drag and drop scope and signal to Source Text Pane to view source Descend Instance or Go To Parent Instance with RM. Click Load Value Changes Icon, then place mouse pointer over signal to view tool tip with signal value at window time. Arrow Buttons The following table shows the actions you can perform with the arrow buttons in the Source Window. Buttons Action Single Yellow Go to previous/next line. Previous works only in postprocessing mode. Go to previous/next breakpoint. Previous works only in postprocessing mode. Double Red Source Window 47 Searching To search for signals in the Source Window, you perform the following tasks: Drag and drop signal to search for into Source Window. Find box is automatically seeded with the signal name, and the first occurrence is highlighted. To find the next/previous occurrence, click the down/up arrow. Control Pane - Show Execution Mode To enable, Display->Show Execution. Yellow arrow shows executed line at current time (interactive mode). Hollow arrows show lines executed in current step (post simulation mode). Dots show execution in this simulation. To Set/Clear Breakpoint, LM on green/red dot to set/clear. Control Pane - Show Coverage Mode To enable, select Display->Show Coverage. Set trace on vhdl files. Displays # of times the simulator executed each line. Dots show execution in this simulation. For Interactive mode, unlink from SIM. 48 Source Window Instance Groups Instance Groups window lets you Trace statement execution, search and clear breakpoints across multiple instances. Switch between instances of current group. Perform debugging using only instances of interest. Instance Groups Command Create Edit->Instance Groups, enter New Instance Group Name, enter instance or drag and drop scope into instance box, click Add, and click OK Edit->Instance Groups, LM on name of Instance Group, Add or Delete Instance, and click OK Edit->Instance Groups, and LM on the name of the Instance Group LM on the Instance Group Icon, and select an Instance Group LM on Select Instance icon LM on desired instance from menu Edit an Instance Group Display Switch Instance Group Switch in Current Group All Group Allows source level debug of the entire design. In interactive mode, line-stepping stops at any line in that model. In post simulation, only those scopes with line-trace enabled are available for line-stepping. Edit Source Edit -> Edit Source then reanalyze and simulate. Source Window 49 Project Browser Window Common tasks in the Project Browser Window are as follows: Manage multiple simulation projects. Graphical entry for new simulation project. Graphical entry for setup, analysis, compilation, and simulation options. Import of existing designs. 50 Project Browser Window ...
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This note was uploaded on 08/23/2009 for the course EE 6303 taught by Professor Mehrdadnourani during the Fall '08 term at University of Texas at Dallas, Richardson.

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