Sept29Le - Lecture 09/29/2008 Kinchit Desai ECSN 3.104...

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Lecture 09/29/2008 Kinchit Desai ECSN 3.104 General Static CMOS Gates Layout issues Euler trail Transistor reordering
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CMOS Static Gates NMOS pull down (PD) network implements the function PMOS network is the complement of the NMOS network Exactly one of the pulldown or pullup n/w is Pull up Pull down OUT = Pull Down IN V DD
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Rule of thumb OR function implemented with transistor in parallel. AND function implemented with transistor in series. Series (PU) = Parallel (PD) Parallel (PD) = Series (PU) PU= Pull up network. PD= Pull down network.
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INV IN OUT = IN V DD OUT IN V DD GND s1 s2 s2 s1 d d
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NAND2 OUT A B s1 s3 d1 s2 s4 A OUT = A B V DD B s1 s2 d1 s3 s4 OUT = A B PULL DOWN FUNCTION PD = A B PULL UP FUNCTION PU = A B A + B V DD GND
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NOR2 GND OUT A B s1 d1 d2 s2 s3 A OUT = A + B V DD B s2 s1 d1 d2 s3 V DD OUT = A +B PULL DOWN FUNCTION PD = A +B PULL UP FUNCTION PU = A+ B A * B
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Complex Gate OUT = A + BC + D NMOS network A B C D
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Complex Gate (cont’d) PMOS network Use De Morgan’s Law: OUT = A + BC + D = A ( B + C) D A B C D
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This note was uploaded on 08/23/2009 for the course EE 6325 taught by Professor Vojin during the Fall '09 term at University of Texas at Dallas, Richardson.

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Sept29Le - Lecture 09/29/2008 Kinchit Desai ECSN 3.104...

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