02_MOSFET_BJT_handout1

02_MOSFET_BJT_handout1 - 1 WLCHEN EE6326 Analog IC Design...

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Unformatted text preview: 1 WLCHEN EE6326 Analog IC Design Fall 2008 Topic 2. Reviews of MOSFET/BJT Device Physics & Models Wenliang Chen Instructor, Ph.D. 2 WLCHEN Outline Reviews of MOSFET/BJT Device Physics & Models CMOS Latchup, Guard-ring and Substrate Isolation 3 WLCHEN Device Symbols M O S F E T B J T PMOS NMOS S G D B D G S B PNP NPN C C E E B B (Enhancement Mode No nature channel exists) (Note: Depletion Mode nature channel exists) 4 WLCHEN MOSFET Structure Poly Oxide G N + N + P_substrate D S L eff L drawn L D NMOS P + B D G S B 5 WLCHEN Cross Section of MOSFET N + N + P + P + P + N + Gate Source Drain Bulk (Body) Bulk (Body) Source Gate Drain NMOS PMOS Substrate Contact Well Contact N-well P+-substrate P-EPI 6 WLCHEN Cross Section of MOSFET in Twin Well Process P + P + P + N + Gate Source Drain SUB Bulk (Body) Source Gate Drain Sensitive NMOS PMOS Well Contact N-well N + N + P-well P+-substrate P-EPI P + N + N + Bulk AVDD ISO **If isolated NMOS is available in process, always use it. 7 WLCHEN Substrate Contact Substrate contact P-type material is biased to the most negative voltage on the chip N-type material is biased to the most positive voltage on the chip Otherwise PN junction is forward biased, MOSFET will not function as desired P N +- +- 8 WLCHEN Cutoff N + N + P-substrate P + Gate Source Drain Bulk (Body) Depletion Region I D = 0, V GS = 0; 9 WLCHEN Threshold Voltage - V T N + N + P-substrate P + Gate Source Drain Bulk (Body) Depletion Region I D = 0, 0 < V GS < V T ; 10 WLCHEN Threshold Voltage - V T N + N + P-substrate P + Gate Source Drain Bulk(Body) Inversion 0, I D T GS V V > 11 WLCHEN Triode/Linear Region P_substrate D S G W N + N + L x V GS > V T & V DS < V GS V T ; ] V 2 1 )V V [(V L W C I 2 DS DS T GS ox n D = V DS I D V GS1 V GS2 V GS3 12 WLCHEN MOSFET as a Controlled Linear Resistor/Switch G D S D S R When V DS <<2(V GS-V T ) MOS can operate as a resistor Whose value is controlled by V GS . DS T GS ox n D 2 DS DS T GS ox n D )V V (V L W C I ] V 2 1 )V V [(V L W C I = ) V (V L W C 1 I V R T GS ox n D DS on = = NMOS Switch for Mixed Signal IC: Ron~100 to 1KW Power IC: Ron < 100mW 13 WLCHEN CMOS Switch A B VB Ron (VDD) Gn A B Gn (GND) VB Ron GND GND VDD (VDD) Gn Channel depletion Channel inversion Dynamic range increases; Charge injection decreases. NMOS Switch 14 WLCHEN Saturation Region Gate P-substrate P + Source Drain Bulk(Body) Pinch-off N + N + V GS > V T & V DS > V GS V T ; 2 T GS ox n D ) V (V L W C 2 1 I = I D V DS V GS1 V GS2 V GS3 Saturation Region Triode Region V G S 1- V T V G S 2- V T V G S 3- V T For the same W/L ratio, the current through NMOS is 2 to 4 time the current through PMOS. n ~ 2x to 4x p....
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02_MOSFET_BJT_handout1 - 1 WLCHEN EE6326 Analog IC Design...

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