05_Irefs_VBG_Vrefs - EE6326 Analog IC Design Fall 2008...

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1 1 WLCHEN EE6326 Analog IC Design – Fall 2008 Topic 5. Current Mirrors & References Band-gap & Voltage References Wenliang Chen, Ph. D. Instructor
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2 2 WLCHEN Outlines Current mirrors –M a t c h i n g • Error terms – Output Impedance – Headroom • Minimum Vout to put all transistors in saturation Current references –C o n s t a n t C u r r e n t – IPTAT (Proportional To Absolute Temp) o n s t a n t G m Band-gap & Voltage references – Thermal Shut Down – Under Voltage Lock Out
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3 3 WLCHEN The First Task for Young Analog Talents To design a Reference Block for Mixed-signal IC Reference Block 1) Current references/mirrors 2) Band-gap + unity gain buffer* 3) Voltage references 4) Thermal shut down 5) Under Voltage Lock Out (UVLO) 6) LDO* * Will be discussed soon
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4 4 WLCHEN V th vs Channel Length L L V th L V th Analog long channel technology (> 1 µ m) Analog/CMOS technology (< 0.35 µ m) Short Channel effects such as deep packet implant to prevent drain-to-source punch through. In general, Vth increases as channel length increases.
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5 5 WLCHEN µ mobility vs temperature & doping As temp. increases, mobility µ, decreases; acoustic phonon dominates The µ (T) ~ µ (300K) x (T/300K) -1.5 Substrate doping increases, µ decreases Temp µ Sub doping µ
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6 6 WLCHEN Current Sources and Sinks Current Sink Current Source Circuits I SS Circuits I 1 V DD
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7 7 WLCHEN Current Mirror Current mirror generates several current sources and current sinks from one single current reference with min. errors Current Mirror Copy Circuits I ref V DD Iout
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8 8 WLCHEN Current Mirror Current mirror generates several current sources and current sinks from one single current reference Assuming M1 & M2 are in saturation , constant (W/L) I Keep L L design Good V - V 1 (W/L) (W/L) ~ V 1 V 1 (W/L) (W/L) ~ V V if V 1 (W/L) V 1 (W/L) I I V 1 ) V (V ) L W ( K' 2 1 I V 1 ) V (V ) L W ( K' 2 1 I 2 1 GS1 out 1 2 DS1 DS2 1 2 T2 T1 DS1 1 DS2 2 REF out DS2 2 T2 GS 2 out DS1 2 T1 GS 1 REF = = + + = + + = + = + = ) ( ) )( ( ; ) ( ) ( ) ( ) ( 1 2 1 2 1 2 2 1 λ I ref V DD Iout W/L M2 M1 W/L
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9 9 WLCHEN Current Mirror Matching Error sources – Threshold voltage mismatch •V GS -V t larger, I D match better – Geometrical mismatch • Smaller unit to reduce errors – Channel length modulation ( λ ) • Ids changes with Vds • Improved with larger output impedance • Headroom trade-off
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10 10 WLCHEN Designing V GST for good current matching The W & L are due to process variations (Etching & diffusion). The Vth is also due to process variation (doping) t GS t D D t t GS ox n 2 t GS ox n t GS ) V (V I (W/L) I D 2 t GS ox n D V V V 2 ) L W ( ) L W ( I I V )( V )(V L W ( C - ) L W ( ) V (V C 2 1 ) V (V ) L W ( I ) V )(V L W ( C 2 1 I t GS D D = = + = = ) µ I D V DD I D1 M1 M0 I D2 M2 V GST =V GS -V t increases V t has lesser effect on I D V GST I D
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11 11 WLCHEN Geometrical Mismatch 1.5%) 4(1 ) 20 0.3 4(1 I I ) 20 0.4 20 0.1 4(1 ) 5 0.1 )(1 20 0.1 4(1 I I 5 0.1 1 20 0.1 1 4 0.1 5 0.1 20 W1 W2 I I D1 D2 D1 D2 D1 D2 m m m m = ± ± ± ± = ± ± = = 0.1μ. 20 W2 0.1μ. 5 W1 ± = ± = I D1 V DD I D2 M2 M1 W2/L W1/L Always Keep L the same to make sure Vth to be as close as possible!
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This note was uploaded on 08/23/2009 for the course EE 6326 taught by Professor Chen-wenliu during the Fall '08 term at University of Texas at Dallas, Richardson.

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05_Irefs_VBG_Vrefs - EE6326 Analog IC Design Fall 2008...

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