EE6326F08HW2 - EE 6326 - Analog Integrated Circuit Design...

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1 EE 6326 - Analog Integrated Circuit Design Homework: HW#2 Due Date: September 20 th , 9:30am in Class 1. Switched Capacitor Resistor (100 points) (AV DD =5V and AV SS =0V) a. NMOS capacitor : (required action is underlined .) Use an NMOS with W=10um, L=2um and mi(finger number)=30, i.e. NMOS size = 30(10/2), from the model library provided. Tie its gate to a supply AV DD . Tie its source, drain and back-gate to AV SS . Use the dc analysis in “spectre” with the option “save DC Operating Point” checked to estimate the gate capacitance (CGG). Please save it as a file then print out the file which shows the “CGG” and other capacitance. Please also plot its gate capacitance values against AV DD which varies from AV SS to AV DD with 0.5V steps. b. MOS switches : (required action is underlined .) Estimate the Ron (on-resistance) of the following switches with 10uA of current passing through the switches: (Please plot your test-benches.) SW1 : NMOS (10/2) with its gate tied to AV DD and its back-gate to AV SS . SW2 : PMOS 4(10/2) with its gate tied to AV SS and its back-gate to AV DD .
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This note was uploaded on 08/23/2009 for the course EE 6326 taught by Professor Chen-wenliu during the Fall '08 term at University of Texas at Dallas, Richardson.

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EE6326F08HW2 - EE 6326 - Analog Integrated Circuit Design...

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